View PIC16LC773-20IP_1286459.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 1999 microchip technology inc. advance information ds30275a-page 1 microcontroller core features: ? high-performance risc cpu ? only 35 single word instructions to learn ? all single cycle instructions except for program branches which are two cycle ? operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle ? 4k x 14 words of program memory, 256 x 8 bytes of data memory (ram) ? interrupt capability (up to 14 internal/external interrupt sources) ? eight level deep hardware stack ? direct, indirect, and relative addressing modes ? power-on reset (por) ? power-up timer (pwrt) and oscillator start-up timer (ost) ? watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation ? programmable code-protection ? power saving sleep mode ? selectable oscillator options ? low-power, high-speed cmos eprom technology ? fully static design ? in-circuit serial programming ? (iscp ) ? wide operating voltage range: 2.5v to 5.5v ? high sink/source current 25/25 ma ? commercial and industrial temperature ranges ? low-power consumption: - < 2 ma @ 5v, 4 mhz - 22.5 m a typical @ 3v, 32 khz -< 1 m a typical standby current pin diagram peripheral features: ? timer0: 8-bit timer/counter with 8-bit prescaler ? timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? two capture, compare, pwm modules ? capture is 16-bit, max. resolution is 12.5 ns, compare is 16-bit, max. resolution is 200 ns, pwm max. resolution is 10-bit ? 12-bit multi-channel analog-to-digital converter ? on-chip absolute bandgap voltage reference generator ? synchronous serial port (ssp) with spi ? (master mode) and i 2 c ? ? universal synchronous asynchronous receiver transmitter, supports high/low speeds and 9-bit address mode (usart/sci) ? parallel slave port (psp) 8-bits wide, with external rd , wr and cs controls ? programmable brown-out detection circuitry for brown-out reset (bor) ? programmable low-voltage detection circuitry 600 mil. pdip, windowed cerdip rb7 rb6 rb5 rb4 rb3/an9/lvdin rb2/an8 rb1/ss rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp ra0/an0 ra1/an1 ra2/an2/v ref -/vrl ra3/an3/v ref +/vrh ra4/t0cki ra5/an4 re0/rd /an5 re1/wr /an6 re2/cs /an7 av dd av ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic16c774 * * * * * * pic16c77x 28/40-pin, 8-bit cmos microcontrollers w/ 12-bit a/d * enhanced features this is an advanced copy of the data sheet and therefore the contents and specifications are subject to change based on device characterization.
pic16c77x ds30275a-page 2 advance information ? 1999 microchip technology inc. pin diagrams mclr /v pp ra0/an0 ra1/an1 ra2/an2/v ref -/vrl ra3/an3/vref+/vrh ra4/t0cki av dd av ss osc1/clkin osc2/clkout rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rb7 rb6 rb5 rb4 rb3/an9/lvdin rb2/an8 rb1/ss rb0/int v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 300 mil. sdip, soic, windowed cerdip, ssop pic16c773 rb3/an9/lvdin rb2/an8 rb1/ss rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7/rx/dt ra4/t0cki ra5/an4 re0/rd/an5 re1/wr/an6 re2/cs/an7 av dd av ss osc1/clkin osc2/clkout rc0/t1oso/t1cki nc ra3/an3/v ref +/vrh ra2/an2/v ref -/vrl ra1/an1 ra0/an0 mclr /v pp nc rb7 rb6 rb5 rb4 nc 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 6 5 4 3 2 1 44 43 42 41 40 28 27 26 25 24 23 22 21 20 19 18 nc rc0/t1oso/t1cki osc2/clkout osc1/clkin av ss av dd re2/cs/an7 re1/wr/an6 re0/rd/an5 ra5/an4 ra4/t0cki rc7/rx/dt rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1/ss rb2/an8 rb3/an9/lvdin rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1 rc1/t1osi/ccp2 nc 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 ra3/an3/v ref +/vrh ra2/an2/v ref -/vrl ra1/an1 ra0/an0 mclr /v pp rb7 rb6 rb5 rb4 nc nc 44 43 42 41 40 39 38 37 36 35 34 22 21 20 19 18 17 16 15 14 13 12 mqfp plcc tqfp pic16c774 pic16c774 rc1/t1osi/ccp2
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 3 key features picmicro? mid-range reference manual (ds33023) pic16c773 pic16c774 operating frequency dc - 20 mhz dc - 20 mhz resets (and delays) por, bor, mclr, wdt (pwrt, ost) por, bor, mclr, wdt (pwrt, ost) program memory (14-bit words) 4k 4k data memory (bytes) 256 256 interrupts 13 14 i/o ports ports a,b,c ports a,b,c,d,e timers 3 3 capture/compare/pwm modules 2 2 serial communications mssp, usart mssp, usart parallel communications psp 12-bit analog-to-digital module 6 input channels 10 input channels instruction set 35 instructions 35 instructions
pic16c77x ds30275a-page 4 advance information ? 1999 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................... 5 2.0 memory organization......................................................................................................... .......................................................... 11 3.0 i/o ports ................................................................................................................... .................................................................... 27 4.0 timer0 module ............................................................................................................... .............................................................. 39 5.0 timer1 module ............................................................................................................... .............................................................. 41 6.0 timer2 module ............................................................................................................... .............................................................. 45 7.0 capture/compare/pwm (ccp) module(s)......................................................................................... .......................................... 47 8.0 master synchronous serial port (mssp) module ................................................................................ ........................................ 53 9.0 addressable universal synchronous asynchronous receiver transmitter (usart) ................................................. ................ 97 10.0 voltage reference module and low-voltage detect............................................................................ ...................................... 113 11.0 analog-to-digital converter (a/d) module ................................................................................... .............................................. 117 12.0 special features of the cpu ................................................................................................ ..................................................... 127 13.0 instruction set summary.................................................................................................... ........................................................ 143 14.0 development support ........................................................................................................ ........................................................ 145 15.0 electrical characteristics................................................................................................. ........................................................... 151 16.0 dc and ac characteristics graphs and tables ................................................................................ ........................................ 173 17.0 packaging information ...................................................................................................... ......................................................... 175 appendix a: revision history .................................................................................................... ..................................................... 187 appendix b: device differences.................................................................................................. ................................................... 187 appendix c: conversion considerations........................................................................................... ............................................. 187 index .......................................................................................................................... ........................................................................ 189 bit/register cross-reference list.............................................................................................. ........................................................ 196 on-line support................................................................................................................ ................................................................. 197 reader response ................................................................................................................ .............................................................. 198 pic16c77x product identification system........................................................................................ ................................................. 199 to our valued customers most current data sheet to obtain the most up-to-date version of this data sheet, please check our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number. e.g., ds30000a is version a of document ds30000. errata an errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the re vi- sion of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchips worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literature center; u.s. fax: (602) 786-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de liter- ature number) you are using. corrections to this data sheet we constantly strive to improve the quality of all our products and documentation. we have spent a great deal of time to ensure that this document is correct. however, we realize that we may have missed a few things. if you find any information that is mi ssing or appears in error, please: ? fill out and mail in the reader response form in the back of this data sheet. ? e-mail us at webmaster@microchip.com. we appreciate your assistance in making this a better document.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 5 1.0 device overview this document contains device-specific information. additional information may be found in the picmicro? mid-range reference manual, (ds33023), which may be obtained from your local microchip sales represen- tative or downloaded from the microchip website. the reference manual should be considered a comple- mentary document to this data sheet, and is highly rec- ommended reading for a better understanding of the device architecture and operation of the peripheral modules. there a two devices (pic16c773 and pic16c774) covered by this datasheet. the pic16c773 devices come in 28-pin packages and the pic16c774 devices come in 40-pin packages. the 28-pin devices do not have a parallel slave port implemented. the following two figures are device block diagrams sorted by pin number; 28-pin for figure 1-1 and 40-pin for figure 1-2 . the 28-pin and 40-pin pinouts are listed in table 1-1 and ta bl e 1 - 2 , respectively. figure 1-1: pic16c773 block diagram eprom program memory 4k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 256 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control osc1/clkin osc2/clkout mclr v dd , v ss porta portb portc ra4/t0cki rb0/int rb7:rb4 rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt 8 8 brown-out reset note 1: higher order bits are from the status register. usart ccp1,2 synchronous timer0 timer1 timer2 serial port ra3/an3/v ref +/vrh ra2/an2/v ref -/vrl ra1/an1 ra0/an0 8 3 timing generation 12-bit adc precision reference rb1/ss rb2/an8 rb3/an9/lvdin low-voltage detect av dd av ss
pic16c77x ds30275a-page 6 advance information ? 1999 microchip technology inc. figure 1-2: pic16c774 block diagram eprom program memory 4k x 14 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers 256 x 8 direct addr 7 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control osc1/clkin osc2/clkout mclr v dd , v ss porta portb portc portd porte ra4/t0cki ra5/an4 rb0/int rb7:rb4 rc0/t1oso/t1cki rc1/t1osi/ccp2 rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt rd7/psp7:rd0/psp0 re0/an5/rd re1/an6/wr re2/an7/cs 8 8 brown-out reset note 1: higher order bits are from the status register. usart ccp1,2 synchronous timer0 timer1 timer2 serial port ra3/an3/v ref +/vrh ra2/an2/v ref -/vrl ra1/an1 ra0/an0 parallel slave port 8 3 timing generation 12-bit adc precision reference rb1/ss rb2/an8 rb3/an9/lvdin low-voltage detect av dd av ss
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 7 table 1-1 pic16c773 pinout description pin name dip, ssop, soic pin# i/o/p type buffer type description osc1/clkin 9 i st/cmos (3) oscillator crystal input/external clock source input. osc2/clkout 10 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, the osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 i/p st master clear (reset) input or programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 2 i/o ttl ra0 can also be analog input0 ra1/an1 3 i/o ttl ra1 can also be analog input1 ra2/an2/v ref -/vrl 4 i/o ttl ra2 can also be analog input2 or negative analog reference voltage input or internal voltage reference low ra3/an3/v ref +/vrh 5 i/o ttl ra3 can also be analog input3 or positive analog reference voltage input or internal voltage reference high ra4/t0cki 6 i/o st ra4 can also be the clock input to the timer0 module. output is open drain type. portb is a bi-directional i/o port. portb can be software pro- grammed for internal weak pull-up on all inputs. rb0/int 21 i/o ttl/st (1) rb0 can also be the external interrupt pin. rb1/ss 22 i/o ttl/st (1) rb1 can also be the ssp slave select rb2/an8 23 i/o ttl rb2 can also be analog input8 rb3/an9/lvdin 24 i/o ttl rb3 can also be analog input9 or the low voltage detect input reference rb4 25 i/o ttl interrupt on change pin. rb5 26 i/o ttl interrupt on change pin. rb6 27 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 28 i/o ttl/st (2) interrupt on change pin. serial programming data. portc is a bi-directional i/o port. rc0/t1oso/t1cki 11 i/o st rc0 can also be the timer1 oscillator output or timer1 clock input. rc1/t1osi/ccp2 12 i/o st rc1 can also be the timer1 oscillator input or capture2 input/ compare2 output/pwm2 output. rc2/ccp1 13 i/o st rc2 can also be the capture1 input/compare1 output/pwm1 output. rc3/sck/scl 14 i/o st rc3 can also be the synchronous serial clock input/output for both spi and i 2 c modes. rc4/sdi/sda 15 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 16 i/o st rc5 can also be the spi data out (spi mode). rc6/tx/ck 17 i/o st rc6 can also be the usart asynchronous transmit or synchronous clock. rc7/rx/dt 18 i/o st rc7 can also be the usart asynchronous receive or synchronous data. av ss 8 p ground reference for a/d converter av dd 7 p positive supply for a/d converter v ss 19 p ground reference for logic and i/o pins. v dd 20 p positive supply for logic and i/o pins. legend: i = input o = output i/o = input/output p = power = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured for the multiplexed function. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured in rc oscillator mode and a cmos input otherwise.
pic16c77x ds30275a-page 8 advance information ? 1999 microchip technology inc. table 1-2 pic16c774 pinout description pin name dip pin# plcc pin# qfp pin# i/o/p type buffer type description osc1/clkin 13 14 30 i st/cmos (4) oscillator crystal input/external clock source input. osc2/clkout 14 15 31 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 2 18 i/p st master clear (reset) input or programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 2 3 19 i/o ttl ra0 can also be analog input0 ra1/an1 3 4 20 i/o ttl ra1 can also be analog input1 ra2/an2/v ref -/vrl 4 5 21 i/o ttl ra2 can also be analog input2 or negative analog reference voltage input or internal voltage reference low ra3/an3/v ref +/vrh 5 6 22 i/o ttl ra3 can also be analog input3 or positive analog reference voltage input or internal voltage reference high ra4/t0cki 6 7 23 i/o st ra4 can also be the clock input to the timer0 timer/ counter. output is open drain type. ra5/an4 7 8 24 i/o ttl ra5 can also be analog input4 portb is a bi-directional i/o port. portb can be soft- ware programmed for internal weak pull-up on all inputs. rb0/int 33 36 8 i/o ttl/st (1) rb0 can also be the external interrupt pin. rb1/ss 34 37 9 i/o ttl/st (1) rb1 can also be the ssp slave select rb2/an8 35 38 10 i/o ttl rb2 can also be analog input8 rb3/an9/lvdin 36 39 11 i/o ttl rb3 can also be analog input9 or input reference for low voltage detect rb4 37 41 14 i/o ttl interrupt on change pin. rb5 38 42 15 i/o ttl interrupt on change pin. rb6 39 43 16 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 40 44 17 i/o ttl/st (2) interrupt on change pin. serial programming data. legend: i = input o = output i/o = input/output p = power = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured for the multiplexed function. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when configured in rc oscillator mode and a cmos input otherwise.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 9 portc is a bi-directional i/o port. rc0/t1oso/t1cki 15 16 32 i/o st rc0 can also be the timer1 oscillator output or a timer1 clock input. rc1/t1osi/ccp2 16 18 35 i/o st rc1 can also be the timer1 oscillator input or capture2 input/compare2 output/pwm2 output. rc2/ccp1 17 19 36 i/o st rc2 can also be the capture1 input/compare1 output/pwm1 output. rc3/sck/scl 18 20 37 i/o st rc3 can also be the synchronous serial clock input/ output for both spi and i 2 c modes. rc4/sdi/sda 23 25 42 i/o st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo 24 26 43 i/o st rc5 can also be the spi data out (spi mode). rc6/tx/ck 25 27 44 i/o st rc6 can also be the usart asynchronous transmit or synchronous clock. rc7/rx/dt 26 29 1 i/o st rc7 can also be the usart asynchronous receive or synchronous data. portd is a bi-directional i/o port or parallel slave port when interfacing to a microprocessor bus. rd0/psp0 19 21 38 i/o st/ttl (3) rd1/psp1 20 22 39 i/o st/ttl (3) rd2/psp2 21 23 40 i/o st/ttl (3) rd3/psp3 22 24 41 i/o st/ttl (3) rd4/psp4 27 30 2 i/o st/ttl (3) rd5/psp5 28 31 3 i/o st/ttl (3) rd6/psp6 29 32 4 i/o st/ttl (3) rd7/psp7 30 33 5 i/o st/ttl (3) porte is a bi-directional i/o port. re0/rd /an5 8 9 25 i/o st/ttl (3) re0 can also be read control for the parallel slave port, or analog input5. re1/wr /an6 9 10 26 i/o st/ttl (3) re1 can also be write control for the parallel slave port, or analog input6. re2/cs /an7 10 11 27 i/o st/ttl (3) re2 can also be select control for the parallel slave port, or analog input7. avss 12 13 29 p ground reference for a/d converter av dd 11 12 28 p positive supply for a/d converter v ss 31 34 6 p ground reference for logic and i/o pins. v dd 32 35 7 p positive supply for logic and i/o pins. nc 1,17,28, 40 12,13, 33,34 these pins are not internally connected. these pins should be left unconnected. table 1-2 pic16c774 pinout description (c ont.d) pin name dip pin# plcc pin# qfp pin# i/o/p type buffer type description legend: i = input o = output i/o = input/output p = power = not used ttl = ttl input st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured for the multiplexed function. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when configured as general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor bus). 4: this buffer is a schmitt trigger input when configured in rc oscillator mode and a cmos input otherwise.
pic16c77x ds30275a-page 10 advance information ? 1999 microchip technology inc. notes:
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 11 2.0 memory organization there are two memory blocks in each of these picmicro ? microcontrollers. each block (pro- gram memory and data memory) has its own bus so that concurrent access can occur. additional information on device memory may be found in the picmicro ? mid-range reference manual, (ds33023). 2.1 program memory organization the pic16c77x picmicros have a 13-bit program counter capable of addressing an 8k x 14 program memory space. each device has 4k x 14 words of pro- gram memory. accessing a location above the physi- cally implemented address will cause a wraparound. the reset vector is at 0000h and the interrupt vector is at 0004h. figure 2-1: program memory map and stack 2.2 data memory organization the data memory is partitioned into multiple banks which contain the general purpose registers and the special function registers. bits rp1 and rp0 are the bank select bits. = 00 ? bank0 = 01 ? bank1 = 10 ? bank2 = 11 ? bank3 each bank extends up to 7fh (128 bytes). the lower locations of each bank are reserved for the special function registers. above the special function regis- ters are general purpose registers, implemented as static ram. all implemented banks contain special function registers. some high use special function registers from one bank may be mirrored in another bank for code reduction and quicker access. 2.2.1 general purpose register file the register file can be accessed either directly, or indi- rectly through the file select register fsr. pc<12:0> 13 0000h 0004h 0005h stack level 1 stack level 8 reset vector interrupt vector on-chip call, return retfie, retlw stack level 2 program memory page 0 page 1 07ffh 0800h 0fffh 1000h 3fffh rp1 rp0 (status<6:5>)
pic16c77x ds30275a-page 12 advance information ? 1999 microchip technology inc. figure 2-2: register file map indirect addr. (*) tmr0 pcl status fsr porta portb portc pclath intcon pir1 tmr1l tmr1h t1con tmr2 t2con sspbuf sspcon ccpr1l ccpr1h ccp1con option_reg pcl status fsr trisa trisb trisc pclath intcon pie1 pcon pr2 sspadd sspstat 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h 7fh ffh bank 0 bank 1 unimplemented data memory locations, read as '0'. * not a physical register. indirect addr. (*) portd porte trisd adresl trise pir2 pie2 rcsta txreg rcreg ccpr2l ccpr2h ccp2con adresh adcon0 txsta spbrg adcon1 general purpose register general purpose register efh f0h accesses 70h-7fh 96 bytes 80 bytes (1) (1) (1) (1) (1) not implemented on pic16c773. lvdcon 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10ah 10bh 10ch 10dh 10eh 10fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11ah 11bh 11ch 11dh 11eh 11fh 120h 17fh bank 2 6fh 70h file address pcl status fsr pclath intcon 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18ah 18bh 18ch 18dh 18eh 18fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19ah 19bh 19ch 19dh 19eh 19fh 1a0h 1ffh bank 3 indirect addr. (*) option_reg 1efh 1f0h accesses 70h - 7fh trisb pcl status fsr pclath intcon indirect addr. (*) tmr0 general purpose register accesses 70h - 7fh portb 80 bytes file address file address file address refcon sspcon2
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 13 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in ta bl e 2 - 1 . the special function registers can be classified into two sets; core (cpu) and peripheral. those registers asso- ciated with the core functions are described in detail in this section. those related to the operation of the peripheral features are described in detail in that peripheral feature section. table 2-1 pic16c77x special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) bank 0 00h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h (4) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 03h (4) status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 04h (4) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta porta5 (5) porta data latch when written: porta<4:0> pins when read --0x 0000 --0u 0000 06h portb portb data latch when written: portb pins when read xxxx 11xx uuuu 11uu 07h portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 08h (5) portd portd data latch when written: portd pins when read xxxx xxxx uuuu uuuu 09h (5) porte re2 re1 re0 ---- -000 ---- -000 0ah (1,4) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 0bh (4) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (3) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 0dh pir2 lvdif Cbclif ccp2if 0--- 0--0 0--- 0--0 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19h txreg usart transmit data register 0000 0000 0000 0000 1ah rcreg usart receive data register 0000 0000 0000 0000 1bh ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu 1ch ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu 1dh ccp2con ccp2x ccp2y ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 1eh adresh a/d high byte result register xxxx xxxx uuuu uuuu 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done chs3 adon 0000 0000 0000 0000 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as 0. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose con tents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the 28-pin devices, always maintain these bits clear. 4: these registers can be addressed from any bank. 5: these registers/bits are not implemented on the 28-pin devices read as '0'.
pic16c77x ds30275a-page 14 advance information ? 1999 microchip technology inc. bank 1 80h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 81h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h (4) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 83h (4) status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 84h (4) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa bit5 (5) porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 87h trisc portc data direction register 1111 1111 1111 1111 88h (5) trisd portd data direction register 1111 1111 1111 1111 89h (5) trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 8ah (1,4) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 8bh (4) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 8ch pie1 pspie (3) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 8dh pie2 lvdie bclie ccp2ie 0--- 0--0 0--- 0--0 8eh pcon por bor ---- --qq ---- --uu 8fh unimplemented 90h unimplemented 91h sspcon2 gcen akstat akdt aken rcen pen rsen sen 0000 0000 0000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 93h sspadd synchronous serial port (i 2 c mode) address register 0000 0000 0000 0000 94h sspstat smp cke d/a psr/w ua bf 0000 0000 0000 0000 95h unimplemented 96h unimplemented 97h unimplemented 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 9ah unimplemented 9bh refcon vrhen vrlen vrhoen vrloen 0000 ---- 0000 ---- 9ch lvdcon bgst lvden lv3 lv2 lv1 lv0 --00 0101 --00 0101 9ah unimplemented 9eh adresl a/d low byte result register xxxx xxxx uuuu uuuu 9fh adcon1 adfm vcfg2 vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 table 2-1 pic16c77x special function register summary (c ont.d) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as 0. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose con tents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the 28-pin devices, always maintain these bits clear. 4: these registers can be addressed from any bank. 5: these registers/bits are not implemented on the 28-pin devices read as '0'.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 15 bank 2 100h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 101h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 102h (4) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 103h (4) status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 104h (4) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 105h unimplemented 106h portb portb data latch when written: portb pins when read xxxx 11xx uuuu 11uu 107h unimplemented 108h unimplemented 109h unimplemented 10ah (1,4) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 10bh (4) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 10ch- 10fh unimplemented bank 3 180h (4) indf addressing this location uses contents of fsr to address data memory (not a physical register) 0000 0000 0000 0000 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 182h (4) pcl program counter's (pc) least significant byte 0000 0000 0000 0000 183h (4) status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 184h (4) fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 185h unimplemented 186h trisb portb data direction register 1111 1111 1111 1111 187h unimplemented 188h unimplemented 189h unimplemented 18ah (1,4) pclath write buffer for the upper 5 bits of the program counter ---0 0000 ---0 0000 18bh (4) intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 18ch- 18fh unimplemented table 2-1 pic16c77x special function register summary (c ont.d) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (2) legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. shaded locations are unimplemented, read as 0. note 1: the upper byte of the program counter is not directly accessible. pclath is a holding register for the pc<12:8> whose con tents are transferred to the upper byte of the program counter. 2: other (non power-up) resets include external reset through mclr and watchdog timer reset. 3: bits pspie and pspif are reserved on the 28-pin devices, always maintain these bits clear. 4: these registers can be addressed from any bank. 5: these registers/bits are not implemented on the 28-pin devices read as '0'.
pic16c77x ds30275a-page 16 advance information ? 1999 microchip technology inc. 2.2.2.1 status register the status register, shown in figure 2-3 , contains the arithmetic status of the alu, the reset status and the bank select bits for data memory. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register because these instructions do not affect the z, c or dc bits from the status register. for other instructions, not affecting any status bits, see the "instruction set summary." figure 2-3: status register (address 03h, 83h, 103h, 183h) note 1: the c and dc bits operate as a borrow and digit borrow bit, respectively, in subtraction. see the sublw and subwf instructions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd z dc c r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: irp : register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) bit 6-5: rp1:rp0 : register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes bit 4: to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit ( addwf , addlw,sublw,subwf instructions) (for borrow the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0: c : carry/borrow bit ( addwf , addlw,sublw,subwf instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 17 2.2.2.2 option_reg register the option_reg register is a readable and writable register which contains various control bits to configure the tmr0 prescaler/wdt postscaler (single assign- able register known also as the prescaler), the external int interrupt, tmr0, and the weak pull-ups on portb. figure 2-4: option_reg register (address 81h, 181h) note: to achieve a 1:1 prescaler assignment for the tmr0 register, assign the prescaler to the watchdog timer. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6: intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5: t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
pic16c77x ds30275a-page 18 advance information ? 1999 microchip technology inc. 2.2.2.3 intcon register the intcon register is a readable and writable regis- ter which contains various enable and flag bits for the tmr0 register overflow, rb port change and external rb0/int pin interrupts. figure 2-5: intcon register (address 0bh, 8bh, 10bh, 18bh) note: interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6: peie : peripheral interrupt enable bit 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts bit 5: t0ie : tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4: iinte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3: rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2: t0if : tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1: intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0: rbif : rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 19 2.2.2.4 pie1 register this register contains the individual enable bits for the peripheral interrupts. figure 2-6: pie1 register (address 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: pspie (1) : parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6: adie : a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5: rcie : usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4: txie : usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3: sspie : synchronous serial port interrupt enable bit 1 = enables the ssp interrupt 0 = disables the ssp interrupt bit 2: ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1: tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0: tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt note 1: pspie is reserved on the 28-pin devices, always maintain this bit clear.
pic16c77x ds30275a-page 20 advance information ? 1999 microchip technology inc. 2.2.2.5 pir1 register this register contains the individual flag bits for the peripheral interrupts. figure 2-7: pir1 register (address 0ch) note: interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: pspif (1) : parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6: adif : a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5: rcif : usart receive interrupt flag bit 1 = the usart receive buffer is full (cleared by reading rcreg) 0 = the usart receive buffer is empty bit 4: txif : usart transmit interrupt flag bit 1 = the usart transmit buffer is empty (cleared by writing to txreg) 0 = the usart transmit buffer is full bit 3: sspif : synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2: ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1: tmr2if : tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0: tmr1if : tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow note 1: pspif is reserved on the 28-pin devices, always maintain this bit clear.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 21 2.2.2.6 pie2 register this register contains the individual enable bits for the ccp2, ssp bus collision, and low voltage detect inter- rupts. figure 2-8: pie2 register (address 8dh) r/w-0 u-0 u-0 u-0 r/w-0 u-0 u-0 r/w-0 lvdie bclie ccp2ie r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7 lvdie : low-voltage detect interrupt enable bit 1 = lvd interrupt is enabled 0 = lvd interrupt is disabled bit 6-4: unimplemented: read as '0' bit 3: bclie : bus collision interrupt enable bit 1 = bus collision interrupt is enabled 0 = bus collision interrupt is disabled bit 2-1: unimplemented: read as '0' bit 0: ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt
pic16c77x ds30275a-page 22 advance information ? 1999 microchip technology inc. 2.2.2.7 pir2 register this register contains the ccp2, ssp bus collision, and low-voltage detect interrupt flag bits. . figure 2-9: pir2 register (address 0dh) note: interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. r/w-0 u-0 u-0 u-0 r/w-0 u-0 u-0 r/w-0 lvdif bclif ccp2if r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: lvdif : low-voltage detect interrupt flag bit 1 = the supply voltage has fallen below the specified lvd voltage (must be cleared in software) 0 = the supply voltage is greater than the specified lvd voltage bit 6-4: unimplemented: read as '0' bit 3: bclif: bus collision interrupt flag bit 1 = a bus collision has occurred while the ssp module configured in i 2 c master was transmitting (must be cleared in software) 0 = no bus collision occurred bit 2-1: unimplemented: read as '0' bit 0: ccp2if : ccp2 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 23 2.2.2.8 pcon register the power control (pcon) register contains a flag bit to allow differentiation between a power-on reset (por) to an external mclr reset or wdt reset. those devices with brown-out detection circuitry con- tain an additional bit to differentiate a brown-out reset condition from a power-on reset condition. figure 2-10: pcon register (address 8eh) note: bor is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bor is clear, indicating a brown-out has occurred. the bor status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the boden bit in the configuration word). u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-1 por bor r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-2: unimplemented: read as '0' bit 1: por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0: bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs)
pic16c77x ds30275a-page 24 advance information ? 1999 microchip technology inc. 2.3 pcl and pclath the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 13 bits wide. the low byte is called the pcl register. this reg- ister is readable and writable. the high byte is called the pch register. this register contains the pc<12:8> bits and is not directly readable or writable. all updates to the pch register go through the pclath register. 2.3.1 stack the stack allows a combination of up to 8 program calls and interrupts to occur. the stack contains the return address from this branch in program execution. midrange devices have an 8 level deep x 13-bit wide hardware stack. the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not modified when the stack is pushed or poped. after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 2.4 program memory paging pic16c77x devices are capable of addressing a con- tinuous 8k word block of program memory. the call and goto instructions provide only 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction the upper 2 bits of the address are provided by pclath<4:3>. when doing a call or goto instruc- tion, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. if a return from a call instruction (or interrupt) is executed, the entire 13-bit pc is pushed onto the stack. therefore, manipulation of the pclath<4:3> bits are not required for the return instructions (which pops the address from the stack).
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 25 the indf register is not a physical register. address- ing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 20h-2fh using indirect addressing is shown in example 2-1 . example 2-1: how to clear ram using indirect addressing movlw 0x20 ;initialize pointer movwf fsr ; to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 2-11 . figure 2-11: direct/indirect addressing note 1: for register file map detail see figure 2-2 . data memory (1) indirect addressing direct addressing bank select location select rp1:rp0 6 0 from opcode irp fsr register 7 0 bank select location select 00 01 10 11 bank 0 bank 1 bank 2 bank 3 ffh 80h 7fh 00h 17fh 100h 1ffh 180h
pic16c77x ds30275a-page 26 advance information ? 1999 microchip technology inc. notes:
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 27 3.0 i/o ports some pins for these i/o ports are multiplexed with an alternate function for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. additional information on i/o ports may be found in the picmicro? mid-range reference manual, (ds33023). 3.1 porta and the trisa register porta is a 6-bit wide bi-directional port for the 40/44 pin devices and is 5-bits wide for the 28-pin devices. porta<5> is not on the 28-pin devices. the corre- sponding data direction register is trisa. setting a trisa bit (=1) will make the corresponding porta pin an input, i.e., put the corresponding output driver in a hi-impedance mode. clearing a trisa bit (=0) will make the corresponding porta pin an output, i.e., put the contents of the output latch on the selected pin. reading the porta register reads the status of the pins whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. pin ra4 is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/t0cki pin is a schmitt trigger input and an open drain output. all other ra port pins have ttl input levels and full cmos output drivers. other porta pins are multiplexed with analog inputs and analog v ref inputs and precision on-board refer- ences (vrl/vrh). the operation of each pin is selected by clearing/setting the control bits in the adcon1 register (a/d control register1). the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 3-1: initializing porta bcf status, rp0 ; clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ; trisa<7:6> are always ; read as '0'. figure 3-1: block diagram of ra3:ra2 pins note: on a power-on reset, these pins are con- figured as analog inputs and read as '0'. data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris latch rd tris rd port v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . analog input mode ttl input buffer to a/d converter vrh, vrl vrhoen, vrloen sense input for vro+, vro- amplifier
pic16c77x ds30275a-page 28 advance information ? 1999 microchip technology inc. figure 3-2: block diagram of ra1:ra0 and ra5 pins figure 3-3: block diagram of ra4/t0cki pin table 3-1 porta functions table 3-2 summary of registers associated with porta data bus q d q ck q d q ck qd en p n wr port wr tris data latch tris latch rd tris rd port v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . analog input mode ttl input buffer to a/d converter data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input note 1: i/o pin has protection diodes to v ss only. q d q ck q d q ck en qd en name bit# buffer function ra0/an0 bit0 ttl input/output or analog input0 ra1/an1 bit1 ttl input/output or analog input1 ra2/an2/v ref -/vrl bit2 ttl input/output or analog input2 or v ref - input or internal reference voltage low ra3/an3/v ref +/vrh bit3 ttl input/output or analog input or v ref + input or output of internal reference voltage high ra4/t0cki bit4 st input/output or external clock input for timer0 output is open drain type ra5/an4 (1) bit5 ttl input/output or analog input legend: ttl = ttl input, st = schmitt trigger input note 1: ra5 is reserved on the 28-pin devices, maintain this bit clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 05h porta (1) ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 85h trisa (1) porta data direction register --11 1111 --11 1111 9fh adcon1 adfm vcfg2 vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta. note 1: porta<5>, trisa<5> are reserved on the 28-pin devices, maintain these bits clear.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 29 3.2 portb and the trisb register portb is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (=1) will make the corresponding portb pin an input, i.e., put the corresponding output driver in a hi-impedance mode. clearing a trisb bit (=0) will make the corresponding portb pin an output, i.e., put the contents of the output latch on the selected pin. example 3-1: initializing portb bcf status, rp0 ; clrf portb ; initialize portb by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (option_reg<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are dis- abled on a power-on reset. the rb0 pin is multiplexed with the external interrupt (rb0/int). figure 3-4: block diagram of rb0 pin the rb1 pin is multiplexed with the ssp module slave select (rb1/ss ). figure 3-5: block diagram of rb1/ss pin the rb2 pin is multiplexed with analog channel 8 (rb2/an8). figure 3-6: block diagram of rb2/an8 pin data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int i/o pin (1) ttl input buffer note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). schmitt trigger buffer tris latch data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port ss input i/o pin (1) ttl input buffer note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). schmitt trigger buffer tris latch data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port to a/d converter i/o pin (1) ttl input buffer note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). tris latch analog input mode
pic16c77x ds30275a-page 30 advance information ? 1999 microchip technology inc. the rb3 pin is multiplexed with analog channel 9 and the low voltage detect input (rb3/an9/lvdin) figure 3-7: block diagram of rb3/an9/lvdin pin four of portbs pins, rb7:rb4, have an interrupt on change feature. only pins configured as inputs can cause this interrupt to occur (i.e. any rb7:rb4 pin con- figured as an output is excluded from the interrupt on change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the mismatch outputs of rb7:rb4 are ored together to generate the rb port change inter- rupt with flag bit rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the inter- rupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition, and allow flag bit rbif to be cleared. the interrupt on change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt on change feature. polling of portb is not recommended while using the interrupt on change feature. figure 3-8: block diagram of rb7:rb4 pins data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port to a/d converter and lvd reference input i/o pin (1) ttl input buffer note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>). tris latch analog input mode or lvd input mode data latch from other rbpu (2) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer pin (1) note 1: i/o pins have diode protection to v dd and v ss . st buffer rb7:rb6 in serial programming mode q3 q1 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (option_reg<7>).
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 31 table 3-3 portb functions table 3-4 summary of registers associated with portb name bit# buffer function rb0/int bit0 ttl/st (1) input/output pin or external interrupt input. internal software programmable weak pull-up. rb1/ss bit1 ttl/st (3) input/output pin or ssp slave select. internal software programmable weak pull-up. rb2/an8 bit2 ttl input/output pin or analog input8. internal software programmable weak pull-up. rb3/an9/lvdin bit3 ttl input/output pin or analog input9 or low-voltage detect input. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming clock. rb7 bit7 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when used as the ssp slave select. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h, 106h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx 11xx uuuu 11uu 86h, 186h trisb portb data direction register 1111 1111 1111 1111 81h, 181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 9fh adcon1 adfm vcfg2 vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 legend: x = unknown, u = unchanged. shaded cells are not used by portb.
pic16c77x ds30275a-page 32 advance information ? 1999 microchip technology inc. 3.3 portc and the trisc register portc is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisc. setting a trisc bit (=1) will make the corresponding portc pin an input, i.e., put the corresponding output driver in a hi-impedance mode. clearing a trisc bit (=0) will make the corresponding portc pin an output, i.e., put the contents of the output latch on the selected pin. portc is multiplexed with several peripheral functions ( ta b l e 3 - 5 ). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. since the tris bit override is in effect while the peripheral is enabled, read-mod- ify-write instructions ( bsf, bcf, xorwf ) with trisc as destination should be avoided. the user should refer to the corresponding peripheral section for the correct tris bit settings. example 3-1: initializing portc bcf status, rp0 ; select bank 0 clrf portc ; initialize portc by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs figure 3-9: portc block diagram (peripheral output override) port/peripheral select (2) data bus wr port wr tris rd data latch tris latch rd tris schmitt trigger q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss port peripheral oe (3) peripheral input i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data and peripheral output. 3: peripheral oe (output enable) is only activated if peripheral select is active.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 33 table 3-5 portc functions table 3-6 summary of registers associated with portc name bit# buffer type function rc0/t1oso/t1cki bit0 st input/output port pin or timer1 oscillator output/timer1 clock input rc1/t1osi/ccp2 bit1 st input/output port pin or timer1 oscillator input or capture2 input/compare2 output/pwm2 output rc2/ccp1 bit2 st input/output port pin or capture1 input/compare1 output/pwm1 output rc3/sck/scl bit3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit5 st input/output port pin or synchronous serial port data output rc6/tx/ck bit6 st input/output port pin or usart asynchronous transmit or synchronous clock rc7/rx/dt bit7 st input/output port pin or usart asynchronous receive or synchronous data legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged.
pic16c77x ds30275a-page 34 advance information ? 1999 microchip technology inc. 3.4 portd and trisd registers this section is applicable to the 40/44-pin devices only. portd is an 8-bit port with schmitt trigger input buff- ers. each pin is individually configurable as an input or output. portd can be configured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit pspmode (trise<4>). in this mode, the input buffers are ttl. figure 3-10: portd block diagram (in i/o port mode) table 3-7 portd functions table 3-8 summary of registers associated with portd data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . q d ck q d ck en qd en name bit# buffer type function rd0/psp0 bit0 st/ttl (1) input/output port pin or parallel slave port bit0 rd1/psp1 bit1 st/ttl (1) input/output port pin or parallel slave port bit1 rd2/psp2 bit2 st/ttl (1) input/output port pin or parallel slave port bit2 rd3/psp3 bit3 st/ttl (1) input/output port pin or parallel slave port bit3 rd4/psp4 bit4 st/ttl (1) input/output port pin or parallel slave port bit4 rd5/psp5 bit5 st/ttl (1) input/output port pin or parallel slave port bit5 rd6/psp6 bit6 st/ttl (1) input/output port pin or parallel slave port bit6 rd7/psp7 bit7 st/ttl (1) input/output port pin or parallel slave port bit7 legend: st = schmitt trigger input ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffer when in parallel slave port mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu 88h trisd portd data direction register 1111 1111 1111 1111 89h trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by portd.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 35 3.5 porte and trise register this section is applicable to the 40/44-pin devices only. porte has three pins re0/rd /an5, re1/wr /an6 and re2/cs /an7, which are individually configurable as inputs or outputs. these pins have schmitt trigger input buffers. i/o porte becomes control inputs for the micropro- cessor port when bit pspmode (trise<4>) is set. in this mode, the user must make sure that the trise<2:0> bits are set (pins are configured as digital inputs). ensure adcon1 is configured for digital i/o. in this mode the input buffers are ttl. figure 3-12 shows the trise register, which also con- trols the parallel slave port operation. porte pins are multiplexed with analog inputs. when selected as an analog input, these pins will read as '0's. trise controls the direction of the re pins, even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. figure 3-11: porte block diagram (in i/o port mode) figure 3-12: trise register (address 89h) note: on a power-on reset these pins are con- figured as analog inputs. data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer q d ck q d ck en qd en i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode bit2 bit1 bit0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7 : ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6: obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5: ibov : input buffer overflow detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4: pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3: unimplemented : read as '0' porte data direction bits bit 2: bit2 : direction control bit for pin re2/cs /an7 1 = input 0 = output bit 1: bit1 : direction control bit for pin re1/wr /an6 1 = input 0 = output bit 0: bit0 : direction control bit for pin re0/rd /an5 1 = input 0 = output
pic16c77x ds30275a-page 36 advance information ? 1999 microchip technology inc. table 3-9 porte functions table 3-10 summary of registers associated with porte name bit# buffer type function re0/rd /an5 bit0 st/ttl (1) input/output port pin or read control input in parallel slave port mode or analog input: rd 1 = not a read operation 0 = read operation. reads portd register (if chip selected) re1/wr /an6 bit1 st/ttl (1) input/output port pin or write control input in parallel slave port mode or analog input: wr 1 = not a write operation 0 = write operation. writes portd register (if chip selected) re2/cs /an7 bit2 st/ttl (1) input/output port pin or chip select control input in parallel slave port mode or analog input: cs 1 = device is not selected 0 = device is selected legend: st = schmitt trigger input ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 09h porte re2re1re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 9fh adcon1 adfm vcfg2 vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by porte.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 37 3.6 parallel slave port the parallel slave port is implemented on the 40/44-pin devices only. portd operates as an 8-bit wide parallel slave port, or microprocessor port when control bit pspmode (trise<4>) is set. in slave mode it is asynchronously readable and writable by the external world through rd control input pin re0/rd and wr control input pin re1/wr . it can directly interface to an 8-bit microprocessor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd to be the rd input, re1/wr to be the wr input and re2/cs to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (set). the configuration bits, pcfg3:pcfg0 (adcon1<3:0>) must be config- ured to make pins re2:re0 as digital i/o. a write to the psp occurs when both the cs and wr lines are first detected low. a read from the psp occurs when both the cs and rd lines are first detected low. figure 3-13: portd and porte block diagram (parallel slave port) figure 3-14: parallel slave port write waveforms data bus wr port rd rdx q d ck en qd en port pin one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr note: i/o pin has protection diodes to v dd and v ss . ttl ttl ttl ttl q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0>
pic16c77x ds30275a-page 38 advance information ? 1999 microchip technology inc. figure 3-15: parallel slave port read waveforms table 3-11 registers associated with parallel slave port address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd port data latch when written: port pins when read xxxx xxxx uuuu uuuu 09h porte re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 0ch pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 9fh adcon1 adfm vcfg2 vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the parallel slave port. q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0>
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 39 4.0 timer0 module the timer0 module timer/counter has the following fea- tures: ? 8-bit timer/counter ? readable and writable ? internal or external clock select ? edge select for external clock ? 8-bit software programmable prescaler ? interrupt on overflow from ffh to 00h figure 4-1 is a simplified block diagram of the timer0 module. additional information on timer modules is available in the picmicro? mid-range reference manual, (ds33023). 4.1 timer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing bit t0cs (option_reg<5>). in timer mode, the timer0 mod- ule will increment every instruction cycle (without pres- caler). if the tmr0 register is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs (option_reg<5>). in counter mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit t0se (option_reg<4>). clearing bit t0se selects the ris- ing edge. restrictions on the external clock input are discussed in below. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. additional information on external clock requirements is available in the picmicro? mid-range reference manual, (ds33023). 4.2 pre scaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer, respectively ( figure 4-2 ). for simplicity, this counter is being referred to as prescaler throughout this data sheet. note that there is only one prescaler available which is mutually exclusively shared between the timer0 module and the watchdog timer. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. the prescaler is not readable or writable. the psa and ps2:ps0 bits (option_reg<3:0>) determine the prescaler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. setting bit psa will assign the prescaler to the watch- dog timer (wdt). when the prescaler is assigned to the wdt, prescale values of 1:1, 1:2, ..., 1:128 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf 1, movwf 1, bsf 1,x ....etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. figure 4-1: timer0 block diagram note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment. note 1: t0cs, t0se, psa, ps2:ps0 (option_reg<5:0>). 2: the prescaler is shared with watchdog timer (refer to figure 4-2 for detailed block diagram). ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 psout (2 cycle delay) psout data bus 8 psa ps2, ps1, ps0 set interrupt flag bit t0if on overflow 3
pic16c77x ds30275a-page 40 advance information ? 1999 microchip technology inc. 4.2.1 switching prescaler assignment the prescaler assignment is fully under software con- trol, i.e., it can be changed on the fly during program execution. 4.3 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h. this overflow sets bit t0if (intcon<2>). the interrupt can be masked by clearing bit t0ie (intcon<5>). bit t0if must be cleared in software by the timer0 module interrupt ser- vice routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep since the timer is shut off during sleep. figure 4-2: block diagram of the timer0/wdt prescaler table 4-1 registers associated with timer0 note: to avoid an unintended device reset, a specific instruction sequence (shown in the picmicro? mid-range reference man- ual, ds33023) must be executed when changing the prescaler assignment from timer0 to the wdt. this sequence must be followed even if the wdt is disabled. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 01h,101h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa porta data direction register --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0. ra4/t0cki t0se pin m u x clkout (=fosc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option_reg<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set flag bit t0if on overflow 8 psa t0cs
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 41 5.0 timer1 module the timer1 module timer/counter has the following fea- tures: ? 16-bit timer/counter (two 8-bit registers; tmr1h and tmr1l) ? readable and writable (both registers) ? internal or external clock select ? interrupt on overflow from ffffh to 0000h ? reset from ccp module trigger timer1 has a control register, shown in figure 5-1 . timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con<0>). figure 5-3 is a simplified block diagram of the timer1 module. additional information on timer modules is available in the picmicro? mid-range reference manual, (ds33023). 5.1 timer1 operation timer1 can operate in one of these modes: ?as a timer ? as a synchronous counter ? as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). in timer mode, timer1 increments every instruction cycle. in counter mode, it increments on every rising edge of the external clock input. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. timer1 also has an internal reset input. this reset can be generated by the ccp module ( section 7.0 ). figure 5-1: t1con: timer1 control register (address 10h) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3: t1oscen : timer1 oscillator enable control bit 1 = oscillator is enabled 0 = oscillator is shut off note: the oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2: t1sync : timer1 external clock input synchronization control bit tmr1cs = 1 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0 this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1: tmr1cs : timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t1cki (on the rising edge) 0 = internal clock (f osc /4) bit 0: tmr1on : timer1 on bit 1 = enables timer1 0 = stops timer1
pic16c77x ds30275a-page 42 advance information ? 1999 microchip technology inc. 5.1.1 timer1 counter operation in this mode, timer1 is being incremented via an exter- nal source. increments occur on a rising edge. after timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment. figure 5-2: timer1 incrementing edge figure 5-3: timer1 block diagram t1cki (default high) t1cki (default low) note: arrows indicate counter increments. tmr1h tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enable oscillator (1) f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 rc0/t1oso/t1cki rc1/t1osi note 1: when the t1oscen bit is cleared, the inverter and feedback resistor are turned off. this eliminates power drain. set flag bit tmr1if on overflow tmr1
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 43 5.2 timer1 oscillator a crystal oscillator circuit is built in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscilla- tor is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. ta bl e 5 - 1 shows the capacitor selection for the timer1 oscillator. the timer1 oscillator is identical to the lp oscillator. the user must provide a software time delay to ensure proper oscillator start-up. table 5-1 capacitor selection for the timer1 oscillator 5.3 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clear- ing tmr1 interrupt enable bit tmr1ie (pie1<0>). 5.4 resetting timer1 using a ccp trigger output if the ccp module is configured in compare mode to generate a special event trigger" (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1 and start an a/d conversion (if the a/d module is enabled). timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a spe- cial event trigger from ccp1, the write will take prece- dence. in this mode of operation, the ccpr1h:ccpr1l regis- ters pair effectively becomes the period register for timer1. table 5-2 registers associated with timer1 as a timer/counter osc type freq c1 c2 lp 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf these values are for design guidance only. crystals tested: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm note 1: higher capacitance increases the stability of oscillator but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. note: the special event triggers from the ccp1 module will not set interrupt flag bit tmr1if (pir1<0>). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer1 module. note 1: these bits are reserved on the 28-pin devices, always maintain these bits clear.
pic16c77x ds30275a-page 44 advance information ? 1999 microchip technology inc. notes:
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 45 6.0 timer2 module the timer2 module timer has the following features: ? 8-bit timer (tmr2 register) ? 8-bit period register (pr2) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4, 1:16) ? software programmable postscaler (1:1 to 1:16) ? interrupt on tmr2 match of pr2 ? ssp module optional use of tmr2 output to gen- erate clock shift timer2 has a control register, shown in figure 6-1 . timer2 can be shut off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. figure 6-2 is a simplified block diagram of the timer2 module. additional information on timer modules is available in the picmicro? mid-range reference manual, (ds33023). 6.1 timer2 operation timer2 can be used as the pwm time-base for pwm mode of the ccp module. the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con<1:0>). the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, (pir1<1>)). the prescaler and postscaler counters are cleared when any of the following occurs: ? a write to the tmr2 register ? a write to the t2con register ? any device reset (power-on reset, mclr reset, watchdog timer reset, or brown-out reset) tmr2 is not cleared when t2con is written. figure 6-1: t2con: timer2 control register (address 12h) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit0 bit 7: unimplemented: read as '0' bit 6-3: toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale ? ? ? 1111 = 1:16 postscale bit 2: tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0: t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16
pic16c77x ds30275a-page 46 advance information ? 1999 microchip technology inc. 6.2 timer2 interrupt the timer2 module has an 8-bit period register pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is ini- tialized to ffh upon reset. 6.3 output of tmr2 the output of tmr2 (before the postscaler) is fed to the synchronous serial port module which optionally uses it to generate shift clock. figure 6-2: timer2 block diagram table 6-1 registers associated with timer2 as a timer/counter comparator tmr2 sets flag tmr2 reg output (1) reset postscaler prescaler pr2 reg 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. to address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 11h tmr2 timer2 modules register 0000 0000 0000 0000 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 92h pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the timer2 module. note 1: these bits are reserved on the 28-pin, always maintain these bits clear.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 47 7.0 capture/compare/pwm (ccp) module(s) each ccp (capture/compare/pwm) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a pwm master/slave duty cycle register. ta bl e 7 - 1 shows the timer resources of the ccp module modes. the operation of ccp1 is identical to that of ccp2, with the exception of the special trigger. therefore, opera- tion of a ccp module in the following sections is described with respect to ccp1. ta bl e 7 - 2 shows the interaction of the ccp modules. ccp1 module capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. all are readable and writable. ccp2 module capture/compare/pwm register2 (ccpr2) is com- prised of two 8-bit registers: ccpr2l (low byte) and ccpr2h (high byte). the ccp2con register controls the operation of ccp2. all are readable and writable. additional information on the ccp module is available in the picmicro? mid-range reference manual, (ds33023). table 7-1 ccp mode - timer resource table 7-2 interaction of two ccp modules figure 7-1: ccp1con register (address 17h) / ccp2con register (address 1dh) ccp mode timer resource capture compare pwm timer1 timer1 timer2 ccpx mode ccpy mode interaction capture capture same tmr1 time-base. capture compare the compare should be configured for the special event trigger, which clears tmr1. compare compare the compare(s) should be configured for the special event trigger, which clears tmr1. pwm pwm the pwms will have the same frequency, and update rate (tmr2 interrupt). pwm capture none pwm compare none u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ccpxx ccpxy ccpxm3 ccpxm2 ccpxm1 ccpxm0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n =value at por reset bit7 bit0 bit 7-6: unimplemented: read as '0' bit 5-4: ccpxx:ccpxy : pwm least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0: ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm off (resets ccpx module) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccpxif bit is set) 1001 = compare mode, clear output on match (ccpxif bit is set) 1010 = compare mode, generate software interrupt on match (ccpxif bit is set, ccpx pin is unaffected) 1011 = compare mode, trigger special event (ccpxif bit is set; ccp1 resets tmr1; ccp2 resets tmr1 and starts an a/d conversion (if a/d module is enabled)) 11xx = pwm mode
pic16c77x ds30275a-page 48 advance information ? 1999 microchip technology inc. 7.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rc2/ccp1. an event is defined as: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit ccp1if (pir1<2>) is set. it must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value will be lost. 7.1.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be config- ured as an input by setting the trisc<2> bit. figure 7-2: capture mode operation block diagram 7.1.2 timer1 mode selection timer1 must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 7.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the flag bit ccp1if following any such change in operating mode. 7.1.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler. example 7-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the false interrupt. example 7-1: changing between capture prescalers clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ; the new prescaler ; mode value and ccp on movwf ccp1con ;load ccp1con with this ; value note: if the rc2/ccp1 is configured as an out- put, a write to the port can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<2>) capture enable qs ccp1con<3:0> rc2/ccp1 prescaler ? 1, 4, 16 and edge detect pin
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 49 7.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc2/ccp1 pin is: ?driven high ? driven low ? remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp1con<3:0>). at the same time, interrupt flag bit ccp1if is set. figure 7-3: compare mode operation block diagram 7.2.1 ccp pin configuration the user must configure the rc2/ccp1 pin as an out- put by clearing the trisc<2> bit. 7.2.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 7.2.3 software interrupt mode when generate software interrupt is chosen the ccp1 pin is not affected. only a ccp interrupt is generated (if enabled). 7.2.4 special event trigger in this mode, an internal hardware trigger is generated which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special trigger output of ccp2 resets the tmr1 register pair, and starts an a/d conversion (if the a/d module is enabled). table 7-3 registers associated with capture, compare, and timer1 ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger (ccp2 only) set flag bit ccp1if (pir1<2>) match rc2/ccp1 trisc<2> ccp1con<3:0> mode select output enable pin special event trigger will: reset timer1, but not set interrupt flag bit tmr1if (pir1<0>), and set bit go/done (adcon0<2>) which starts an a/d conversion note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the data latch. note: the special event trigger from the ccp2 module will not set interrupt flag bit tmr1if (pir1<0>). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1register xxxx xxxx uuuu uuuu 10h t1con t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on --00 0000 --uu uuuu 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by capture and timer1. note 1: bits pspie and pspif are reserved on the 28-pin, always maintain these bits clear.
pic16c77x ds30275a-page 50 advance information ? 1999 microchip technology inc. 7.3 pwm mode in pulse width modulation (pwm) mode, the ccp1 pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 7-4 shows a simplified block diagram of the ccp module in pwm mode. for a step by step procedure on how to set up the ccp module for pwm operation, see section 7.3.3 . figure 7-4: simplified pwm block diagram a pwm output ( figure 7-5 ) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/ period). figure 7-5: pwm output 7.3.1 pwm period the pwm period is specified by writing to the pr2 reg- ister. the pwm period can be calculated using the fol- lowing formula: pwm period = [(pr2) + 1] ? 4 ? t osc ? (tmr2 prescale value) pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ?tmr2 is cleared ? the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) ? the pwm duty cycle is latched from ccpr1l into ccpr1h 7.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available: the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) ? tosc ? (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2 con- catenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. maximum pwm resolution (bits) for a given pwm frequency: for an example pwm period and duty cycle calcu- lation, see the picmicro? mid-range reference manual, (ds33023). note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time-base. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 6.0 ) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different fre- quency than the pwm output. note: if the pwm duty cycle value is longer than the pwm period the ccp1 pin will not be cleared. log ( f pwm log(2) f osc ) bits =
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 51 7.3.3 set-up for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 regis- ter. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 7-4 example pwm frequencies and resolutions at 20 mhz table 7-5 registers associated with pwm and timer2 pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescaler (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 5.5 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 87h trisc portc data direction register 1111 1111 1111 1111 11h tmr2 timer2 modules register 0000 0000 0000 0000 92h pr2 timer2 modules period register 1111 1111 1111 1111 12h t2con toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 15h ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu 16h ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu 17h ccp1con ccp1x ccp1y ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by pwm and timer2. note 1: bits pspie and pspif are reserved on the 28-pin, always maintain these bits clear.
pic16c77x ds30275a-page 52 advance information ? 1999 microchip technology inc. notes:
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 53 8.0 master synchronous serial port (mssp) module the master synchronous serial port (mssp) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the mssp module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c?)
pic16c77x ds30275a-page 54 advance information ? 1999 microchip technology inc. figure 8-1: sspstat: sync serial port status register (address: 94h) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf r =readable bit w =writable bit u =unimplemented bit, read as 0 - n =value at por reset bit7 bit0 bit 7: smp : sample bit spi master mode 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode smp must be cleared when spi is used in slave mode in i 2 c master or slave mode: 1= slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0= slew rate control enabled for high speed mode (400 khz) bit 6: cke : spi clock edge select ( figure 8-6 , figure 8-8 , and figure 8-9 ) ckp = 0 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck ckp = 1 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5: d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4: p : stop bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared) 1 = indicates that a stop bit has been detected last (this bit is '0' on reset) 0 = stop bit was not detected last bit 3: s : start bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared) 1 = indicates that a start bit has been detected last (this bit is '0' on reset) 0 = start bit was not detected last bit 2: r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not ack bit. in i 2 c slave mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress. oring this bit with sen, rsen, pen, rcen, or aken will indicate if the mssp is in idle mode bit 1: ua : update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0: bf : buffer full status bit receive (spi and i 2 c modes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit (i 2 c mode only) 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 55 figure 8-2: sspcon: sync serial port control register (address 14h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 r = readable bit w = writable bit - n = value at por reset bit7 bit0 bit 7: wcol : write collision detect bit master mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision slave mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6: sspov : receive overflow indicator bit in spi mode 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. in slave mode, the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. (must be cleared in software). 0 = no overflow in i 2 c mode 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a "dont care" in transmit mode. (must be cleared in software). 0 = no overflow bit 5: sspen : synchronous serial port enable bit in both modes, when enabled, these pins must be properly configured as input or output. in spi mode 1 = enables serial port and configures sck, sdo, sdi, and ss as the source of the serial port pins 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode 1 = enables the serial port and configures the sda and scl pins as the source of the serial port pins 0 = disables serial port and configures these pins as i/o port pins bit 4: ckp : clock polarity select bit in spi mode 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c slave mode sck release control 1 = enable clock 0 = holds clock low (clock stretch) (used to ensure data setup time) in i 2 c master mode unused in this mode bit 3-0: sspm3:sspm0 : synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc / (4 * (sspadd+1) ) 1xx1 = reserved 1x1x = reserved
pic16c77x ds30275a-page 56 advance information ? 1999 microchip technology inc. figure 8-3: sspcon2: sync serial port control register2 (address 91h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen akstat akdt aken rcen pen rsen sen r =readable bit w =writable bit u =unimplemented bit, read as 0 - n =value at por reset bit7 bit0 bit 7: gcen : general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspsr. 0 = general call address disabled. bit 6: akstat : acknowledge status bit (in i 2 c master mode only) in master transmit mode: 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5: akdt : acknowledge data bit (in i 2 c master mode only) in master receive mode: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. 1 = not acknowledge 0 = acknowledge bit 4: aken : acknowledge sequence enable bit (in i 2 c master mode only). in master receive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit akdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3: rcen : receive enable bit (in i 2 c master mode only). 1 = enables receive mode for i 2 c 0 = receive idle bit 2: pen : stop condition enable bit (in i 2 c master mode only). sck release control 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1: rsen : repeated start condition enabled bit (in i 2 c master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle. bit 0: sen : start condition enabled bit (in i 2 c master mode only) 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle. note: for bits aken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling), and the sspbuf may not be written (or writes to the sspbuf are disabled).
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 57 8.1 spi mode the spi mode allows 8-bits of data to be synchro- nously transmitted and received simultaneously. all four modes of spi are supported. to accomplish com- munication, typically three pins are used: ? serial data out (sdo) ? serial data in (sdi) ? serial clock (sck) additionally, a fourth pin may be used when in a slave mode of operation: ?slave select (ss ) 8.1.1 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon<5:0> and sspstat<7:6>). these control bits allow the following to be specified: ? master mode (sck is the clock output) ? slave mode (sck is the clock input) ? clock polarity (idle state of sck) ? data input sample phase (middle or end of data output time) ? clock edge (output data on rising/falling edge of sck) ? clock rate (master mode only) ? slave select mode (slave mode only) figure 8-4 shows the block diagram of the mssp mod- ule when in spi mode. figure 8-4: mssp block diagram (spi mode) the mssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr, until the received data is ready. once the 8-bits of data have been received, that byte is moved to the sspbuf register. then the buffer full detect bit bf (sspstat<0>) and the interrupt flag bit sspif (pir1<3>) are set. this double buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored, and the write collision detect bit wcol (sspcon<7>) will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the ssp- buf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit, bf (sspstat<0>), indicates when the ssp- buf has been loaded with the received data (transmis- sion is complete). when the sspbuf is read, bit bf is cleared. this data may be irrelevant if the spi is only a transmitter. generally the mssp interrupt is used to read write internal data bus sspsr reg sspbuf reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr data direction bit 2 smp:cke sdi sdo ss sck
pic16c77x ds30275a-page 58 advance information ? 1999 microchip technology inc. determine when the transmission/reception has com- pleted. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 8-1 shows the loading of the sspbuf (sspsr) for data transmission. example 8-1: loading the sspbuf (sspsr) register the sspsr is not directly readable or writable, and can only be accessed by addressing the sspbuf register. additionally, the mssp status register (sspstat) indi- cates the various status conditions. 8.1.2 enabling spi i/o to enable the serial port, mssp enable bit, sspen (sspcon<5>) must be set. to reset or reconfigure spi mode, clear bit sspen, re-initialize the sspcon reg- isters, and then set bit sspen. this configures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed. that is: ? sdi is automatically controlled by the spi module ? sdo must have trisc<5> cleared ? sck (master mode) must have trisc<3> cleared ? sck (slave mode) must have trisc<3> set ?ss must have trisa<5> set any serial port function that is not desired may be over- ridden by programming the corresponding data direc- tion (tris) register to the opposite value. 8.1.3 typical connection figure 8-5 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their pro- grammed clock edge, and latched on the opposite edge of the clock. both processors should be programmed to same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: ? master sends data slave sends dummy data ? master sends data slave sends data ? master sends dummy data slave sends data figure 8-5: spi master/slave connection bsf status, rp0 ;specify bank 1 loop btfss sspstat, bf ;has data been ;received ;(transmit ;complete)? goto loop ;no bcf status, rp0 ;specify bank 0 movf sspbuf, w ;w reg = contents ;of sspbuf movwf rxdata ;save in user ram movf txdata, w ;w reg = contents ; of txdata movwf sspbuf ;new data to xmit serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm3:sspm0 = 00xx b serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm3:sspm0 = 010x b serial clock
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 59 8.1.4 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 8-5 ) is to broad- cast data by the software protocol. in master mode the data is transmitted/received as soon as the sspbuf register is written to. if the spi module is only going to receive, the sdo output could be disabled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a line activity monitor. the clock polarity is selected by appropriately program- ming bit ckp (sspcon<4>). this then would give waveforms for spi communication as shown in figure 8-6 , figure 8-8 , and figure 8-9 where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the follow- ing: ?f osc /4 (or t cy ) ?f osc /16 (or 4 ? t cy ) ?f osc /64 (or 16 ? t cy ) ? timer2 output/2 this allows a maximum bit clock frequency (at 20 mhz) of 8.25 mhz. figure 8-6 shows the waveforms for master mode. when cke = 1, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 8-6: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit0 sdi sspif (smp = 1) (smp = 0) (smp = 1) cke = 1) cke = 0) cke = 1) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (cke = 0) (cke = 1) next q4 cycle after q2
pic16c77x ds30275a-page 60 advance information ? 1999 microchip technology inc. 8.1.5 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched the interrupt flag bit sspif (pir1<3>) is set. while in slave mode the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received the device will wake-up from sleep. 8.1.6 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ). the pin must not be driven low for the ss pin to function as an input. trisa<5> must be set. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. external pull-up/ pull-down resistors may be desirable, depending on the application. when the spi module resets, the bit counter is forced to 0. this can be done by either forcing the ss pin to a high level or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver the sdo pin can be configured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus conflict. figure 8-7: slave synchronization waveform note: when the spi module is in slave mode with ss pin control enabled, (ssp- con<3:0> = 0100 ) the spi module will reset if the ss pin is set to v dd . note: if the spi is used in slave mode with cke = '1', then ss pin control must be enabled. sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 sdo bit7 bit6 bit7 sspif interrupt (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss flag bit0 bit7 bit0 next q4 cycle after q2
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 61 figure 8-8: spi slave mode waveform (cke = 0) figure 8-9: spi slave mode waveform (cke = 1) sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif interrupt (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss flag optional next q4 cycle after q2 sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif interrupt (smp = 0) cke = 1) cke = 1) (smp = 0) write to sspbuf sspsr to sspbuf ss flag not optional next q4 cycle after q2
pic16c77x ds30275a-page 62 advance information ? 1999 microchip technology inc. 8.1.7 sleep operation in master mode all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from sleep. after the device returns to normal mode, the module will continue to transmit/ receive data. in slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode, and data to be shifted into the spi transmit/receive shift register. when all 8-bits have been received, the mssp interrupt flag bit will be set and if enabled will wake the device from sleep. 8.1.8 effects of a reset a reset disables the mssp module and terminates the current transfer. table 8-1 registers associated with spi operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 por, bor mclr , wdt 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 94h sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the ssp in spi mode. note 1: these bits are reserved on the 28-pin devices, always maintain these bits clear.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 63 8.2 mssp i 2 c operation the mssp module in i 2 c mode fully implements all master and slave functions (including general call sup- port) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master func- tion). the mssp module implements the standard mode specifications as well as 7-bit and 10-bit address- ing. refer to application note an578, "use of the ssp module in the i 2 c multi-master environment." a "glitch" filter is on the scl and sda pins when the pin is an input. this filter operates in both the 100 khz and 400 khz modes. in the 100 khz mode, when these pins are an output, there is a slew rate control of the pin that is independant of device frequency. figure 8-10: i 2 c slave mode block diagram figure 8-11: i 2 c master mode block diagram two pins are used for data transfer. these are the scl pin, which is the clock, and the sda pin, which is the data. the sda and scl pins that are automatically configured when the i 2 c mode is enabled. the ssp module functions are enabled by setting ssp enable bit sspen (sspcon<5>). the mssp module has six registers for i 2 c operation. they are the: ? ssp control register (sspcon) ? ssp control register2 (sspcon2) ? ssp status register (sspstat) ? serial receive/transmit buffer (sspbuf) ? ssp shift register (sspsr) - not directly acces- sible ? ssp address register (sspadd) the sspcon register allows control of the i 2 c opera- tion. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: ?i 2 c slave mode (7-bit address) ?i 2 c slave mode (10-bit address) ?i 2 c master mode, clock = osc/4 (sspadd +1) before selecting any i 2 c mode, the scl and sda pins must be programmed to inputs by setting the appropri- ate tris bits. selecting an i 2 c mode, by setting the sspen bit, enables the scl and sda pins to be used as the clock and data lines in i 2 c mode. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) scl shift clock msb lsb sda read write sspsr reg match detect sspadd reg start and stop bit detect / generate sspbuf reg internal data bus addr match set/clear s bit clear/set p bit (sspstat reg) scl shift clock msb lsb sda baud rate generator 7 sspadd<6:0> and and set sspif
pic16c77x ds30275a-page 64 advance information ? 1999 microchip technology inc. the sspstat register gives the status of the data transfer. this information includes detection of a start (s) or stop (p) bit, specifies if the received byte was data or address if the next byte is the comple- tion of 10-bit address, and if this will be a read or write data transfer. sspbuf is the register to which the transfer data is written to or read from. the sspsr register shifts the data in or out of the device. in receive operations, the sspbuf and sspsr create a doubled buffered receiver. this allows reception of the next byte to begin before reading the last byte of received data. when the complete byte is received, it is transferred to the sspbuf register and flag bit sspif is set. if another complete byte is received before the sspbuf register is read, a receiver overflow has occurred and bit sspov (sspcon<6>) is set and the byte in the sspsr is lost. the sspadd register holds the slave address. in 10-bit mode, the user needs to write the high byte of the address ( 1111 0 a9 a8 0 ). following the high byte address match, the low byte of the address needs to be loaded (a7:a0). 8.2.1 slave mode in slave mode, the scl and sda pins must be config- ured as inputs. the mssp module will override the input state with the output data when required (slave- transmitter). when an address is matched or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse, and then load the sspbuf register with the received value currently in the sspsr register. there are certain conditions that will cause the mssp module not to give this ack pulse. these are if either (or both): a) the buffer full bit bf (sspstat<0>) was set before the transfer was received. b) the overflow bit sspov (sspcon<6>) was set before the transfer was received. if the bf bit is set, the sspsr register value is not loaded into the sspbuf, but bit sspif and sspov are set. ta bl e 8 - 2 shows what happens when a data trans- fer byte is received, given the status of bits bf and sspov. the shaded cells show the condition where user software did not properly clear the overflow condi- tion. flag bit bf is cleared by reading the sspbuf reg- ister while bit sspov is cleared through software. the scl clock input must have a minimum high and low time for proper operation. the high and low times of the i 2 c specification as well as the requirement of the mssp module is shown in timing parameter #100 and parameter #101 of the electrical specifications. 8.2.1.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start con- dition, the 8-bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register on the falling edge of the 8th scl pulse. b) the buffer full bit, bf is set on the falling edge of the 8th scl pulse. c) an ack pulse is generated. d) ssp interrupt flag bit, sspif (pir1<3>) is set (interrupt is generated if enabled) - on the falling edge of the 9th scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address the first byte would equal 1111 0 a9 a8 0 , where a9 and a8 are the two msbs of the address. the sequence of events for a 10-bit address is as follows, with steps 7- 9 for slave-transmit- ter: 1. receive first (high) byte of address (bits sspif, bf, and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the first (high) byte of address. this will clear bit ua and release the scl line. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif. note: following the repeated start condition (step 7) in 10-bit mode, the user only needs to match the first 7-bit address. the user does not update the sspadd for the second half of the address.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 65 8.2.1.2 slave reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte overflow condition exists, then no acknowledge (ack ) pulse is given. an overflow con- dition is defined as either bit bf (sspstat<0>) is set or bit sspov (sspcon<6>) is set. an ssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in soft- ware. the sspstat register is used to determine the status of the received byte. table 8-2 data transfer received byte actions 8.2.1.3 slave transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit, and the scl pin is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then the scl pin should be enabled by setting bit ckp (ssp- con<4>). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretching the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time ( figure 8-13 ). an ssp interrupt is generated for each data transfer byte. the sspif flag bit must be cleared in software, and the sspstat register is used to determine the sta- tus of the byte tranfer. the sspif flag bit is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the ack pulse from the master- receiver is latched on the rising edge of the ninth scl input pulse. if the sda line was high (not ack ), then the data transfer is complete. when the not ack is latched by the slave, the slave logic is reset and the slave then monitors for another occurrence of the start bit. if the sda line was low (ack ), the transmit data must be loaded into the sspbuf register, which also loads the sspsr register. then the scl pin should be enabled by setting the ckp bit. figure 8-12: i 2 c waveforms for reception (7-bit address) note: the sspbuf will be loaded if the sspov bit is set and the bf flag is cleared. if a read of the sspbuf was performed, but the user did not clear the state of the sspov bit before the next receive occured. the ack is not sent and the ssp- buf is updated. status bits as data transfer is received sspsr ? sspbuf generate ack pulse set bit sspif (ssp interrupt occurs if enabled) bf sspov 00 yes yes yes 1 0 no no yes 1 1 no no yes 0 1 ye s no ye s note 1: shaded cells show the conditions where the user software did not properly clear the overflow condition. p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 56 7 89 123 4 bus master terminates transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w =0 receiving address sspif bf (sspstat<0>) sspov (sspcon<6>) ack ack is not sent. not
pic16c77x ds30275a-page 66 advance information ? 1999 microchip technology inc. figure 8-13: i 2 c waveforms for transmission (7-bit address) sda scl sspif bf (sspstat<0>) ckp (sspcon<4>) a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 not ack transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written-to before the ckp bit can be set) r/w = 0
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 67 figure 8-14: i 2 c slave-transmitter (10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 1 111 0a9a8 a7 a6a5a4a3a2a1a0 11110 a8 r/w =1 ack ack r/w = 0 ack receive first byte of address cleared in software master sends nack a9 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated. ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated. sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf flag sr cleared in software write of sspbuf initiates transmit cleared in software transmit is complete ckp has to be set for clock to be released bus master terminates transfer
pic16c77x ds30275a-page 68 advance information ? 1999 microchip technology inc. figure 8-15: i 2 c slave-receiver (10-bit address) sda scl sspif bf (sspstat<0>) s 1 234 56 7 89 1 2345 67 89 1 2345 7 89 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 d7d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software bus master terminates transfer d2 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated with low byte of address. ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack r/w = 1 cleared in software dummy read of sspbuf to clear bf flag read of sspbuf clears bf flag cleared by hardware when sspadd is updated with high byte of address.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 69 8.2.2 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowl- edge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all 0s with r/w = 0 the general call address is recognized when the gen- eral call enable bit (gcen) is enabled (sspcon2<7> is set). following a start-bit detect, 8-bits are shifted into sspsr and the address is compared against sspadd, and is also compared to the general call address, fixed in hardware. if the general call address matches, the sspsr is transfered to the sspbuf, the bf flag is set (eighth bit), and on the falling edge of the ninth bit (ack bit) the sspif flag is set. when the interrupt is serviced. the source for the interrupt can be checked by reading the contents of the sspbuf to determine if the address was device spe- cific or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match, and the ua bit is set (sspstat<1>). if the general call address is sampled when gcen is set while the slave is config- ured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set, and the slave will begin receiving data after the acknowledge ( figure 8-16 ). figure 8-16: slave mode general call address sequence (7 or 10-bit mode) sda scl s sspif bf sspov cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address gcen receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack, set interrupt flag '0' '1' (sspstat<0>) (sspcon<6>) (sspcon2<7>)
pic16c77x ds30275a-page 70 advance information ? 1999 microchip technology inc. 8.2.3 sleep operation while in sleep mode, the i 2 c module can receive addresses or data, and when an address match or complete byte transfer occurs wake the processor from sleep (if the ssp interrupt is enabled). 8.2.4 effects of a reset a reset diables the ssp module and terminates the current transfer. table 8-3 registers associated with i 2 c operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 por, bor mclr , wdt 0bh, 8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 0dh pir2 lvdif bclif ccp2if 0--- 0--0 0--- 0--0 8dh pie2 lvdie bclie ccp2ie 0--- 0--0 0--- 0--0 13h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 14h sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 91h sspcon2 gcen akstat akdt aken rcen pen rsen sen 0000 0000 0000 0000 94h sspstat smp cke d/a ps r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by the ssp in i 2 c mode. note 1: these bits are reserved on the 28-pin devices, always maintain these bits clear. 2: these bits are reserved on these devices, always maintain these bits clear.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 71 8.2.5 master mode master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is dis- abled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle with both the s and p bits clear. in master mode, the scl and sda lines are manipu- lated by the mssp hardware. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): ? start condition ? stop condition ? data transfer byte transmitted/received ? acknowledge transmit ? repeated start figure 8-17: ssp block diagram (i 2 c master mode) read write sspsr start bit, stop bit, start bit detect, sspbuf internal data bus set/reset, s, p, wcol (sspstat) shift clock msb lsb sda acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif reset akstat, pen (sspcon2) rate generator sspm3:sspm0,
pic16c77x ds30275a-page 72 advance information ? 1999 microchip technology inc. 8.2.6 multi-master operation in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when bit p (sspstat<4>) is set, or the bus is idle with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will gener- ate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored, for abitration, to see if the signal level is the expected output level. this check is performed in hard- ware, with the result placed in the bclif bit. the states where arbitration can be lost are: ? address transfer ? data transfer ? a start condition ? a repeated start condition ? an acknowledge condition 8.2.7 i 2 c master operation support master mode is enabled by setting and clearing the appropriate sspm bits in sspcon and by setting the sspen bit. once master mode is enabled, the user has six options. - assert a start condition on sda and scl. - assert a repeated start condition on sda and scl. - write to the sspbuf register initiating trans- mission of data/address. - generate a stop condition on sda and scl. - configure the i 2 c port to receive data. - generate an acknowledge condition at the end of a received byte of data. 8.2.7.4 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a trans- fer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic '0'. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case the r/w bit will be logic '1'. thus the first byte transmitted is a 7-bit slave address followed by a '1' to indicate receive bit. serial data is received via sda while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator used for spi mode operation is now used to set the scl clock frequency for either 100 khz, 400 khz, or 1 mhz i 2 c operation. the baud rate generator reload value is contained in the lower 7 bits of the sspadd register. the baud rate generator will automatically begin counting on a write to the ssp- buf. once the given operation is complete (i.e. trans- mission of the last data bit is followed by ack), the internal clock will automatically stop counting and the scl pin will remain in its last state a typical transmit sequence would go as follows: a) the user generates a start condition by setting the start enable bit (sen) in sspcon2. b) sspif is set. the module will wait the required start time before any other operation takes place. c) the user loads the sspbuf with address to transmit. d) address is shifted out the sda pin until all 8 bits are transmitted. e) the mssp module shifts in the ack bit from the slave device, and writes its value into the sspcon2 register ( sspcon2<6>). f) the module generates an interrupt at the end of the ninth clock cycle by setting sspif. g) the user loads the sspbuf with eight bits of data. h) data is shifted out the sda pin until all 8 bits are transmitted. note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance: the user is not allowed to initiate a start condition, and immediately write the sspbuf register to initiate transmission before the start condition is complete. in this case the sspbuf will not be written to, and the wcol bit will be set, indicating that a write to the sspbuf did not occur.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 73 i) the mssp module shifts in the ack bit from the slave device, and writes its value into the sspcon2 register ( sspcon2<6>). j) the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. k) the user generates a stop condition by setting the stop enable bit pen in sspcon2. l) interrupt is generated once the stop condition is complete. 8.2.8 baud rate generator in i 2 c master mode, the reload value for the brg is located in the lower 7 bits of the sspadd register ( figure 8-18 ). when the brg is loaded with this value, the brg counts down to 0 and stops until another reload has taken place. the brg count is decremented twice per instruction cycle (t cy ) on the q2 and q4 clock. in i 2 c master mode, the brg is reloaded automatically. if clock arbitration is taking place for instance, the brg will be reloaded when the scl pin is sampled high ( figure 8-19 ). figure 8-18: baud rate generator block diagram figure 8-19: baud rate generator timing with clock arbitration sspm3:sspm0 brg down counter clkout fosc/4 sspadd<6:0> sspm3:sspm0 scl reload control reload sda scl scl de-asserted but slave holds dx-1 dx brg scl is sampled high, reload takes place, and brg starts its count. 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements (on q2 and q4 cycles)
pic16c77x ds30275a-page 74 advance information ? 1999 microchip technology inc. 8.2.9 i 2 c master mode start condition timing to initiate a start condition, the user sets the start condition enable bit, sen (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate genera- tor is re-loaded with the contents of sspadd<6:0>, and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition, and causes the s bit (sspstat<3>) to be set. follow- ing this, the baud rate generator is reloaded with the contents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2<0>) will be automatically cleared by hardware, the baud rate generator is suspended leaving the sda line held low, and the start condition is complete. 8.2.9.5 wcol status flag if the user writes the sspbuf when an start sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). figure 8-20: first start bit timing note: if at the beginning of start condition the sda and scl pins are already sampled low, or if during the start condition the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag (bclif) is set, the start condition is aborted, and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1, at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here. set s bit (sspstat<3>) and sets sspif bit
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 75 figure 8-21: start condition flowchart idle mode sen (sspcon2<0> = 1) bus collision detected, set bclif, sda = 1? load brg with ye s brg rollover? force sda = 0, load brg with sspadd<6:0>, no ye s force scl = 0, clear sen set s bit. sspadd<6:0> scl = 1? sda = 0? no ye s brg rollover? no clear sen start condition done, no ye s reset brg scl= 0? no ye s scl = 0? no ye s reset brg release scl, sspen = 1, sspcon<3:0> = 1000 and set sspif
pic16c77x ds30275a-page 76 advance information ? 1999 microchip technology inc. 8.2.10 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2<1>) is programmed high and the i 2 c mod- ule is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded with the contents of sspadd<6:0>, and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be de-asserted (brought high). when scl is sampled high the baud rate generator is re-loaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda is low) for one t brg while scl is high. following this, the rsen bit in the sspcon2 register will be automatically cleared, and the baud rate generator is not reloaded, leaving the sda pin held low. as soon as a start con- dition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed-out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 8.2.10.6 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). figure 8-22: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. note 2: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low to high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data "1". note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here. falling edge of ninth clock end of xmit at completion of start bit, hardware clear rsen bit 1st bit set s (sspstat<3>) t brg t brg sda = 1, sda = 1, scl(no change) scl = 1 occurs here. t brg t brg t brg and set sspif
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 77 figure 8-23: repeated start condition flowchart (page 1) idle mode, sspen = 1, force scl = 0 scl = 0? release sda, load brg with scl = 1? no ye s no ye s brg no ye s release scl sspcon<3:0> = 1000 rollover? sspadd<6:0> load brg with sspadd<6:0> (clock arbitration) a b c sda = 1? no ye s start rsen = 1 bus collision, set bclif, release sda, clear rsen
pic16c77x ds30275a-page 78 advance information ? 1999 microchip technology inc. figure 8-24: repeated start condition flowchart (page 2) force sda = 0, load brg with sspadd<6:0> ye s repeated start clear rsen, ye s brg rollover? brg rollover? ye s sda = 0? no scl = 1? no b set s c a no no ye s force scl = 0, reset brg set sspif. scl = '0'? reset brg no ye s condition done,
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 79 8.2.11 i 2 c master mode transmission transmission of a data byte, a 7-bit address, or either half of a 10-bit address is accomplished by simply writ- ing a value to sspbuf register. this action will set the buffer full flag (bf) and allow the baud rate generator to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time spec). scl is held low for one baud rate gener- ator roll over count (t brg ). data should be valid before scl is released high (see data setup time spec). when the scl pin is released high, it is held that way for t brg , the data on the sda pin must remain stable for that duration and some hold time after the next fall- ing edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda allowing the slave device being addressed to respond with an ack bit during the ninth bit time, if an address match occurs or if data was received properly. the status of ack is read into the akdt on the falling edge of the ninth clock. if the mas- ter receives an acknowledge, the acknowledge status bit (akstat) is cleared. if not, the bit is set. after the ninth clock the sspif is set, and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf leaving scl low and sda unchanged ( figure 8-26 ). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the fall- ing edge of the eighth clock the master will de-assert the sda pin allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the akstat status bit (sspcon2<6>). fol- lowing the falling edge of the ninth clock transmission of the address, the sspif is set, the bf flag is cleared, and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 8.2.11.7 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 8.2.11.8 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e. sspsr is still shifting out a data byte), then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). wcol must be cleared in software. 8.2.11.9 akstat status flag in transmit mode, the akstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0), and is set when the slave does not acknowl- edge (ack = 1). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data.
pic16c77x ds30275a-page 80 advance information ? 1999 microchip technology inc. figure 8-25: master transmit flowchart idle mode num_clocks = 0, release sda so slave can drive ack, num_clocks load brg with sda = current data bit ye s brg rollover? no brg no ye s force scl = 0 = 8? ye s no ye s brg rollover? no force scl = 1, stop brg scl = 1? load brg with count high time rollover? no read sda and place into akstat bit (sspcon2<6>) force scl = 0, scl = 1? sda = data bit? no ye s ye s rollover? no ye s stop brg, force scl = 1 (clock arbitration) (clock arbitration) num_clocks = num_clocks + 1 bus collision detected set bclif, hold prescale off, ye s no bf = 1 force bf = 0 sspadd<6:0>, start brg count, load brg with sspadd<6:0>, start brg count sspadd<6:0>, load brg with count scl high time sspadd<6:0>, sda = data bit? ye s no clear xmit enable scl = 0? no ye s reset brg write sspbuf set sspif
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 81 figure 8-26: i 2 c master mode timing (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7d6d5d4d3d2d1d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from ssp interrupt after start condition sen cleared by hardware. s sspbuf written with 7 bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave clear akstat bit sspcon2<6> akstat in sspcon2 = 1 cleared in software sspbuf written pen cleared in software r/w
pic16c77x ds30275a-page 82 advance information ? 1999 microchip technology inc. 8.2.12 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting, and on each rollover, the state of the scl pin changes (high to low/ low to high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf flag is set, the sspif is set, and the baud rate generator is sus- pended from counting, holding scl low. the ssp is now in idle state, awaiting the next command. when the buffer is read by the cpu, the bf flag is automati- cally cleared. the user can then send an acknowledge bit at the end of reception, by setting the acknowledge sequence enable bit, aken (sspcon2<4>). 8.2.12.10 bf status flag in receive operation, bf is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when sspbuf is read. 8.2.12.11 sspov status flag in receive operation, sspov is set when 8 bits are received into the sspsr, and the bf flag is already set from a previous reception. 8.2.12.12 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e. sspsr is still shifting in a data byte), then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). note: the ssp module must be in an idle state before the rcen bit is set, or the rcen bit will be disregarded.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 83 figure 8-27: master receiver flowchart idle mode num_clocks = 0, release sda force scl=0, ye s no brg rollover? release scl ye s no scl = 1? load brg with ye s no brg rollover? (clock arbitration) load brg w/ start count sspadd<6:0>, start count. sample sda, shift data into sspsr num_clocks = num_clocks + 1 ye s num_clocks = 8? no force scl = 0, set sspif, set bf. move contents of sspsr into sspbuf, clear rcen. rcen = 1 sspadd<6:0>, scl = 0? ye s no
pic16c77x ds30275a-page 84 advance information ? 1999 microchip technology inc. figure 8-28: i 2 c master mode timing (reception 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1) write to sspbuf occurs here ack from slave master configured as a receiver by programming sspcon2<3>, (rcen = 1) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0, scl = 1 while cpu (sspstat<0>) ack last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set aken start acknowledge sequence sspov is set because sspbuf is still full sda = akdt = 1 rcen cleared automatically rcen = 1 start next receive write to sspcon2<4> to start acknowledge sequence sda = akdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif aken begin start condition cleared in software sda = akdt = 0
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 85 8.2.13 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, aken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit is presented on the sda pin. if the user wishes to generate an acknowledge, then the akdt bit should be cleared. if not, the user should set the akdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ), and the scl pin is de-asserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the aken bit is automati- cally cleared, the baud rate generator is turned off, and the ssp module then goes into idle mode. ( figure 8- 29 ) 8.2.13.13 wcol status flag if the user writes the sspbuf when an acknowledege sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). figure 8-29: acknowledge sequence waveform note: t brg = one baud rate generator period. sda scl set sspif at the end acknowledge sequence starts here, write to sspcon2 aken automatically cleared cleared in t brg t brg of receive ack 8 aken = 1, akdt = 0 d0 9 sspif software set sspif at the end of acknowledge sequence cleared in software
pic16c77x ds30275a-page 86 advance information ? 1999 microchip technology inc. figure 8-30: acknowledge flowchart idle mode force scl = 0 ye s no scl = 0? drive akdt bit ye s no brg rollover? (sspcon2<5>) onto sda pin, load brg with sspadd<6:0>, start count. force scl = 1 ye s no scl = 1? no akdt = 1? load brg with no brg rollover? sspadd <6:0>, start count. no sda = 1? bus collision detected, set bclif, ye s force scl = 0, (clock arbitration) clear aken no scl = 0? reset brg clear aken, set aken release scl, ye s ye s ye s set sspif
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 87 8.2.14 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit pen (sspcon2<2>). at the end of a receive/trans- mit the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low . when the sda line is sam- pled low, the baud rate generator is reloaded and counts down to 0. when the baud rate generator times out, the scl pin will be brought high, and one t brg (baud rate generator rollover count) later, the sda pin will be de-asserted. when the sda pin is sampled high while scl is high, the p bit (sspstat<4>) is set. a t brg later the pen bit is cleared and the sspif bit is set ( figure 8-31 ). whenever the firmware decides to take control of the bus, it will first determine if the bus is busy by checking the s and p bits in the sspstat register. if the bus is busy, then the cpu can be interrupted (notified) when a stop bit is detected (i.e. bus is free). 8.2.14.14 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesnt occur). figure 8-31: stop condition receive or transmit mode scl sda sda asserted low before rising edge of clock write to sspcon2 set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set t brg to setup stop condition. ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set
pic16c77x ds30275a-page 88 advance information ? 1999 microchip technology inc. figure 8-32: stop condition flowchart idle mode, sspen = 1, force sda = 0 scl doesnt change sda = 0? de-assert scl, scl = 1 scl = 1? no ye s start brg no ye s brg sda going from 0 to 1 while scl = 1 no ye s set sspif, release sda, start brg stop condition done sspcon<3:0> = 1000 rollover? no brg rollover? ye s p bit set? no ye s bus collision detected, set bclif, clear pen start brg no ye s brg rollover? (clock arbitration) pen = 1 pen cleared.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 89 8.2.15 clock arbitration clock arbitration occurs when the master, during any receive, transmit, or repeated start/stop condition, de- asserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate gen- erator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sam- pled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device ( figure 8-33 ). 8.2.16 sleep operation while in sleep mode, the i 2 c module can receive addresses or data, and when an address match or complete byte transfer occurs wake the processor from sleep ( if the ssp interrupt is enabled). 8.2.17 effects of a reset a reset disables the ssp module and terminates the current transfer. figure 8-33: clock arbitration timing in master transmit mode scl sda brg overflow, release scl, if scl = 1 load brg with sspadd<6:0>, and start count brg overflow occurs, release scl, slave device holds scl low. scl = 1 brg starts counting clock high interval. scl line sampled once every machine cycle (t osc 4). hold off brg until scl is sampled high. t brg t brg t brg to measure high time interval
pic16c77x ds30275a-page 90 advance information ? 1999 microchip technology inc. 8.2.18 multi -master communication, bus collision, and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a '1' on sda by letting sda float high and another master asserts a '0'. when the scl pin floats high, data should be stable. if the expected data on sda is a '1' and the data sampled on the sda pin = '0', then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif and reset the i 2 c port to its idle state. ( figure 8-34 ). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are de-asserted, and the sspbuf can be written to. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop, or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are de-asserted, and the respective control bits in the sspcon2 register are cleared. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communica- tion by asserting a start condition. the master will continue to monitor the sda and scl pins, and if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit, regardless of where the trans- mitter left off when bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat reg- ister, or the bus is idle and the s and p bits are cleared. figure 8-34: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high data doesnt match what is driven bus collision has occurred. set bus collision interrupt. by the master. by master data changes while scl = 0
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 91 8.2.18.15 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition ( figure 8-35 ). b) scl is sampled low before sda is asserted low. ( figure 8-36 ). during a start condition both the sda and the scl pins are monitored. if: the sda pin is already low or the scl pin is already low, then: the start condition is aborted, and the bclif flag is set, and the ssp module is reset to its idle state ( figure 8-35 ). the start condition begins with the sda and scl pins de-asserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early ( figure 8-37 ). if however a '1' is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0, and during this time, if the scl pins is sampled as '0', a bus collision does not occur. at the end of the brg count the scl pin is asserted low. figure 8-35: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address follow- ing the start condition, and if the address is the same, arbitration must be allowed to continue into the data portion, repeated start, or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1, scl=1 sda = 0, scl = 1 bclif s sspif sda = 0, scl = 1 sspif and bclif are cleared in software. sspif and bclif are cleared in software. set bclif, set bclif. start condition.
pic16c77x ds30275a-page 92 advance information ? 1999 microchip technology inc. figure 8-36: bus collision during start condition (scl = 0) figure 8-37: brg reset due to sda collision during start condition sda scl sen bus collision occurs, set bclif. scl = 0 before sda = 0, set sen, enable start sequence if sda = 1, scl = 1 t brg t brg sda = 0, scl = 1 bclif s sspif interrupts cleared in software. bus collision occurs, set bclif. scl = 0 before brg time out, '0' '0' '0' '0' sda scl sen set s set sen, enable start sequence if sda = 1, scl = 1 less than t brg t brg sda = 0, scl = 1 bclif s sspif s interrupts cleared in software. set sspif sda = 0, scl = 1 sda pulled low by other master. reset brg and assert sda scl pulled low after brg timeout set sspif '0'
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 93 8.2.18.16 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indi- cating that another master is attempting to trans- mit a data 1. when the user de-asserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0>, and counts down to 0. the scl pin is then de- asserted, and when sampled high, the sda pin is sam- pled. if sda is low, a bus collision has occurred (i.e. another master is attempting to transmit a data 0). if however sda is sampled high then the brg is reloaded and begins counting. if sda goes from high to low before the brg times out, no bus collision occurs, because no two masters can assert sda at exactly the same time. if, however, scl goes from high to low before the brg times out and sda has not already been asserted, then a bus collision occurs. in this case, another master is attempting to transmit a data 1 during the repeated start condition. if at the end of the brg time out both scl and sda are still high, the sda pin is driven low, the brg is reloaded, and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is com- plete ( figure 8-38 ). figure 8-38: bus collision during a repeated start condition (case 1) figure 8-39: bus collision during repeated start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0, set bclif and release sda and scl cleared in software '0' '0' '0' '0' sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl t brg t brg '0' '0' '0' '0'
pic16c77x ds30275a-page 94 advance information ? 1999 microchip technology inc. 8.2.18.17 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been de-asserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is de-asserted, scl is sam- pled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allow to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to 0. after the brg times out sda is sam- pled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data '0'. if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data '0' ( figure 8-40 ). figure 8-40: bus collision during a stop condition (case 1) figure 8-41: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif '0' '0' '0' '0' sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high set bclif '0' '0'
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 95 8.3 connection considerations for i 2 c bus for standard-mode i 2 c bus devices, the values of resistors r p r s in figure 8-42 depends on the following parameters ? supply voltage ? bus capacitance ? number of connected devices (input current + leakage current). the supply voltage limits the minimum value of resistor r p due to the specified minimum sink current of 3 ma at v ol max = 0.4v for the specified output stages. for example, with a supply voltage of v dd = 5v+ 10% and v ol max = 0.4v at 3 ma, r p min = (5.5-0.4)/0.003 = 1.7 k w. v dd as a function of r p is shown in figure 8-42. the desired noise margin of 0.1v dd for the low level limits the maximum value of r s . series resistors are optional and used to improve esd susceptibility. the bus capacitance is the total capacitance of wire, connections, and pins. this capacitance limits the max- imum value of r p due to the specified rise time ( figure 8-42 ). the smp bit is the slew rate control enabled bit. this bit is in the sspstat register, and controls the slew rate of the i/o pins when in i 2 c mode (master or slave). figure 8-42: sample device configuration for i 2 c bus r p r p v dd + 10% sda scl note: i 2 c devices with input levels related to v dd must have one common supply line to which the pull up resistor is also connected. device c b =10 - 400 pf r s r s
pic16c77x ds30275a-page 96 advance information ? 1999 microchip technology inc. notes:
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 97 9.0 addressable universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also known as a serial com- munications interface or sci). the usart can be con- figured as a full duplex asynchronous system that can communicate with peripheral devices such as crt ter- minals and personal computers, or it can be configured as a half duplex synchronous system that can commu- nicate with peripheral devices such as a/d or d/a inte- grated circuits, serial eeproms etc. the usart can be configured in the following modes: ? asynchronous (full duplex) ? synchronous - master (half duplex) ? synchronous - slave (half duplex) bit spen (rcsta<7>), and bits trisc<7:6>, have to be set in order to configure pins rc6/tx/ck and rc7/ rx/dt as the universal synchronous asynchronous receiver transmitter. the usart module also has a multi-processor com- munication capability using 9-bit address detection. figure 9-1: txsta: transmit status and control register (address 98h) r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync brgh trmt tx9d r = readable bit w = writable bit u = unimplemented bit, read as 0 - n =value at por reset bit7 bit0 bit 7: csrc : clock source select bit asynchronous mode dont care synchronous mode 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6: tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5: txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4: sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3: unimplemented: read as '0' bit 2: brgh : high baud rate select bit asynchronous mode 1 = high speed 0 = low speed synchronous mode unused in this mode bit 1: trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0: tx9d : 9th bit of transmit data. can be parity bit.
pic16c77x ds30275a-page 98 advance information ? 1999 microchip technology inc. figure 9-2: rcsta: receive status and control register (address 18h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d r = readable bit w = writable bit u = unimplemented bit, read as 0 - n =value at por reset bit7 bit0 bit 7: spen : serial port enable bit 1 = serial port enabled (configures rc7/rx/dt and rc6/tx/ck pins as serial port pins) 0 = serial port disabled bit 6: rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5: sren : single receive enable bit asynchronous mode dont care synchronous mode - master 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode - slave unused in this mode bit 4: cren : continuous receive enable bit asynchronous mode 1 = enables continuous receive 0 = disables continuous receive synchronous mode 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3: adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1) 1 = enables address detection, enable interrupt and load of the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received, and ninth bit can be used as parity bit bit 2: ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1: oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0: rx9d : 9th bit of received data (can be parity bit)
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 99 9.1 usart baud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. in asynchronous mode bit brgh (txsta<2>) also controls the baud rate. in synchronous mode bit brgh is ignored. ta bl e 9 - 1 shows the formula for computation of the baud rate for different usart modes which only apply in master mode (internal clock). given the desired baud rate and fosc, the nearest inte- ger value for the spbrg register can be calculated using the formula in ta bl e 9 - 1 . from this, the error in baud rate can be determined. example 9-1 shows the calculation of the baud rate error for the following conditions: f osc = 16 mhz desired baud rate = 9600 brgh = 0 sync = 0 example 9-1: calculating baud rate error it may be advantageous to use the high baud rate (brgh = 1) even for slower baud clocks. this is because the f osc /(16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before output- ting the new baud rate. 9.1.1 sampling the data on the rc7/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. table 9-1 baud rate formula table 9-2 registers associated with baud rate generator desired baud rate = fosc / (64 (x + 1)) 9600 = 16000000 /(64 (x + 1)) x= ? 25.042 ? = 25 calculated baud rate=16000000 / (64 (25 + 1)) =9615 error = (calculated baud rate - desired baud rate) desired baud rate = (9615 - 9600) / 9600 =0.16% sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64(x+1)) (synchronous) baud rate = f osc /(4(x+1)) baud rate= f osc /(16(x+1)) na x = value in spbrg (0 to 255) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used by the brg.
pic16c77x ds30275a-page 100 advance information ? 1999 microchip technology inc. table 9-3 baud rates for synchronous mode table 9-4 baud rates for asynchronous mode (brgh = 0) baud rate (k) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3na- -na- -na- -na- - 1.2na- -na- -na- -na- - 2.4na- -na- -na- -na- - 9.6 na - - na - - 9.766 +1.73 255 9.622 +0.23 185 19.2 19.53 +1.73 255 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 76.8 76.92 +0.16 64 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 96 96.15 +0.16 51 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 300 294.1 -1.96 16 307.69 +2.56 12 312.5 +4.17 7 298.3 -0.57 5 500 500 0 9 500 0 7 500 0 4 na - - high 5000 - 0 4000 - 0 2500 - 0 1789.8 - 0 low 19.53 - 255 15.625 - 255 9.766 - 255 6.991 - 255 baud rate (k) f osc = 5.0688 mhz 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3na - - na- - na - - na- -0.303+1.1426 1.2 na - - na - - na - - 1.202 +0.16 207 1.170 -2.48 6 2.4 na - - na - - na - - 2.404 +0.16 103 na - - 9.6 9.6 0 131 9.615 +0.16 103 9.622 +0.23 92 9.615 +0.16 25 na - - 19.2 19.2 0 65 19.231 +0.16 51 19.04 -0.83 46 19.24 +0.16 12 na - - 76.8 79.2 +3.13 15 76.923 +0.16 12 74.57 -2.90 11 83.34 +8.51 2 na - - 96 97.48 +1.54 12 1000 +4.17 9 99.43 +3.57 8 na - - na - - 300 316.8 +5.60 3 na - - 298.3 -0.57 2 na - - na - - 500na - - na- - na - - na- - na- - high 1267 - 0 100 - 0 894.9 - 0 250 - 0 8.192 - 0 low 4.950 - 255 3.906 - 255 3.496 - 255 0.9766 - 255 0.032 - 255 baud rate (k) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3na--na --na --na-- 1.2 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129 1.203 +0.23 92 2.4 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64 2.380 -0.83 46 9.6 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15 9.322 -2.90 11 19.2 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 76.8 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1 na - - 96 104.2 +8.51 2 na - - na - - na - - 300 312.5 +4.17 0 na - - na - - na - - 500na- -na- -na- -na- - high 312.5 - 0 250 - 0 156.3 - 0 111.9 - 0 low 1.221 - 255 0.977 - 255 0.6104 - 255 0.437 - 255 baud rate (k) f osc = 5.0688 mhz 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 0.31 +3.13 255 0.3005 -0.17 207 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1 1.2 1.2 0 65 1.202 +1.67 51 1.190 -0.83 46 1.202 +0.16 12 na - - 2.4 2.4 0 32 2.404 +1.67 25 2.432 +1.32 22 2.232 -6.99 6 na - - 9.6 9.9 +3.13 7 na - - 9.322 -2.90 5 na - - na - - 19.2 19.8 +3.13 3 na - - 18.64 -2.90 2 na - - na - - 76.8 79.2 +3.13 0 na - - na - - na - - na - - 96na--na--na--na--na-- 300na - - na- - na- - na- - na- - 500na - - na- - na- - na- - na- - high 79.2 - 0 62.500 - 0 55.93 - 0 15.63 - 0 0.512 - 0 low 0.3094 - 255 3.906 - 255 0.2185 - 255 0.0610 - 255 0.0020 - 255
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 101 table 9-5 baud rates for asynchronous mode (brgh = 1) baud rate (k) f osc = 20 mhz spbrg value (decimal) 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.16 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 9.6 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64 9.520 -0.83 46 19.2 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32 19.454 +1.32 22 38.4 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15 37.286 -2.90 11 57.6 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10 55.930 -2.90 7 115.2 113.636 -1.36 10 111.111 -3.55 8 125 +8.51 4 111.860 -2.90 3 250 250 0 4 250 0 3 na - - na - - 625 625 0 1 na - - 625 0 0 na - - 1250 1250 0 0 na - - na - - na - - baud rate (k) f osc = 5.068 mhz spbrg value (decimal) 4 mhz spbrg value (decimal) 3.579 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error kbaud % error 9.6 9.6 0 32 na - - 9.727 +1.32 22 8.928 -6.99 6 na - - 19.2 18.645 -2.94 16 1.202 +0.17 207 18.643 -2.90 11 20.833 +8.51 2 na - - 38.4 39.6 +3.12 7 2.403 +0.13 103 37.286 -2.90 5 31.25 -18.61 1 na - - 57.6 52.8 -8.33 5 9.615 +0.16 25 55.930 -2.90 3 62.5 +8.51 0 na - - 115.2 105.6 -8.33 2 19.231 +0.16 12 111.860 -2.90 1 na - - na - - 250 na - - na - - 223.721 -10.51 0 na - - na - - 625na - - na- - na- - na- - na- - 1250 na - - na - - na - - na - - na - -
pic16c77x ds30275a-page 102 advance information ? 1999 microchip technology inc. 9.2 usart asynchronous mode in this mode, the usart uses standard nonreturn-to- zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8-bits. an on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the usart transmits and receives the lsb first. the usarts transmitter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock either x16 or x64 of the bit shift rate, depending on bit brgh (txsta<2>). parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing bit sync (txsta<4>). the usart asynchronous module consists of the fol- lowing important elements: ? baud rate generator ? sampling circuit ? asynchronous transmitter ? asynchronous receiver 9.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 9-3 . the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and flag bit txif (pir1<4>) is set. this interrupt can be enabled/disabled by setting/clearing enable bit txie ( pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicated the sta- tus of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. sta- tus bit trmt is a read only bit which is set when the tsr register is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. steps to follow when setting up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh. ( section 9.1 ) 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set transmit bit tx9. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts trans- mission). figure 9-3: usart transmit block diagram note 1: the tsr register is not mapped in data memory so it is not available to the user. note 2: flag bit txif is set when enable bit txen is set. txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 103 figure 9-4: asynchronous transmission figure 9-5: asynchronous transmission (back to back) table 9-6 registers associated with asynchronous transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous transmission. note 1: bits pspie and pspif are reserved on the 28-pin devices, always maintain these bits clear. word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions.
pic16c77x ds30275a-page 104 advance information ? 1999 microchip technology inc. 9.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 9-6 . the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . the usart module has a special provision for multi- processor communication. when the rx9 bit is set in the rcsta register, 9-bits are received and the ninth bit is placed in the rx9d status bit of the rsta register. the port can be programmed such that when the stop bit is received, the serial port interrupt will only be acti- vated if the rx9d bit = 1. this feature is enabled by setting the adden bit rcsta<3> in the rcsta regis- ter. this feature can be used in a multi-processor sys- tem as follows: a master processor intends to transmit a block of data to one of many slaves. it must first send out an address byte that identifies the target slave. an address byte is identified by the rx9d bit being a 1 (instead of a 0 for a data byte). if the adden bit is set in the slaves rcsta register, all data bytes will be ignored. how- ever, if the ninth received bit is equal to a 1, indicating that the received byte is an address, the slave will be interrupted and the contents of the rsr register will be transferred into the receive buffer. this allows the slave to be interrupted only by addresses, so that the slave can examine the received byte to see if it is addressed. the addressed slave will then clear its adden bit and prepare to receive data bytes from the master. when adden is set, all data bytes are ignored. fol- lowing the stop bit, the data will not be loaded into the receive buffer, and no interrupt will occur. if another byte is shifted into the rsr register, the previous data byte will be lost. the adden bit will only take effect when the receiver is configured in 9-bit mode. the receiver block diagram is shown in figure 9-6 . once asynchronous mode is selected, reception is enabled by setting bit cren (rcsta<4>). 9.2.3 setting up 9-bit mode with address detect steps to follow when setting up an asynchronous reception with address detect enabled: ? initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh. ? enable the asynchronous serial port by clearing bit sync and setting bit spen. ? if interrupts are desired, then set enable bit rcie. ? set bit rx9 to enable 9-bit reception. ? set adden to enable address detect. ? enable the reception by setting enable bit cren. ? flag bit rcif will be set when reception is com- plete, and an interrupt will be generated if enable bit rcie was set. ? read the rcsta register to get the ninth bit and determine if any error occurred during reception. ? read the 8-bit received data by reading the rcreg register, to determine if the device is being addressed. ? if any error occurred, clear the error by clearing enable bit cren. ? if the device has been addressed, clear the adden bit to allow data bytes and address bytes to be read into the receive buffer, and interrupt the cpu.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 105 figure 9-6: usart receive block diagram figure 9-7: asynchronous reception with address detect x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 ? 64 ? 16 or stop start (8) 7 1 0 rx9 rx9 adden rx9 adden rsr<8> enable load of receive buffer 8 8 start bit bit1 bit0 bit8 bit0 stop bit start bit bit8 stop bit rc7/rx/dt (pin) load rsr read rcif word 1 rcreg note: this timing diagram shows a data byte followed by an address byte. the data byte is not read into the rcreg (receive bu ffer) bit8 = 0, data byte bit8 = 1, address byte because adden = 1.
pic16c77x ds30275a-page 106 advance information ? 1999 microchip technology inc. figure 9-8: asynchronous reception with address byte first table 9-7 registers associated with asynchronous reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous reception. note 1: bits pspie and pspif are reserved on the 28-pin devices, always maintain these bits clear. start bit bit1 bit0 bit8 bit0 stop bit start bit bit8 stop bit rc7/rx/dt (pin) load rsr read rcif word 1 rcreg bit8 = 1, address byte bit8 = 0, data byte note: this timing diagram shows an address byte followed by a data byte. the data byte is not read into the rcreg (receive bu ffer) because aden was not updated and still = 0.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 107 9.3 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner i.e. transmission and reception do not occur at the same time. when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta<4>). in addition enable bit spen (rcsta<7>) is set in order to configure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit csrc (txsta<7>). 9.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 9-3 . the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one tcycle), the txreg is empty and inter- rupt bit, txif (pir1<4>) is set. the interrupt can be enabled/disabled by setting/clearing enable bit txie (pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit trmt (txsta<1>) shows the status of the tsr register. trmt is a read only bit which is set when the tsr is empty. no inter- rupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate ( section 9.1 ). 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. table 9-8 registers associated with synchronous master transmission address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous master transmission. note 1: bits pspie and pspif are reserved on the 28-pin devices, always maintain these bits clear.
pic16c77x ds30275a-page 108 advance information ? 1999 microchip technology inc. figure 9-9: synchronous transmission figure 9-10: synchronous transmission (through txen) bit 0 bit 1 bit 7 word 1 q1q2 q3q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2 q3q4 q3q4 q1q2 q3q4 q1q2 q3q4 q1q2 q3 q4 q1 q2q3 q4 q1 q2q3 q4 q1 q2q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit (interrupt flag) trmt txen bit '1' '1' note: sync master mode; spbrg = '0'. continuous transmission of two 8-bit words. word 2 trmt bit write word1 write word2 rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit0 bit1 bit2 bit6 bit7 txen bit
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 109 9.3.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either enable bit sren (rcsta<5>) or enable bit cren (rcsta<4>). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, then only a single word is received. if enable bit cren is set, the reception is continuous until cren is cleared. if both bits are set then cren takes precedence. steps to follow when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate. ( section 9.1 ) 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, then set enable bit rcie. 5. if 9-bit reception is desired, then set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception set bit cren. 7. interrupt flag bit rcif will be set when reception is complete and an interrupt will be generated if enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. table 9-9 registers associated with synchronous master reception figure 9-11: synchronous reception (master mode, sren) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous master reception. note 1: bits pspie and pspif are reserved on the 28-pin devices, always maintain these bits clear. cren bit rc7/rx/dt pin rc6/tx/ck pin write to bit sren sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with bit sren = '1' and bit brgh = '0'. q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 '0' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 '0' q1 q2 q3 q4
pic16c77x ds30275a-page 110 advance information ? 1999 microchip technology inc. 9.4 usart synchronous slave mode synchronous slave mode differs from the master mode in the fact that the shift clock is supplied externally at the rc6/tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit csrc (txsta<7>). 9.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit txif will now be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep and if the global interrupt is enabled, the program will branch to the inter- rupt vector (0004h). steps to follow when setting up a synchronous slave transmission: 1. enable the synchronous slave serial port by set- ting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, then set enable bit txie. 4. if 9-bit transmission is desired, then set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 9.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical except in the case of the sleep mode. also, bit sren is a don't care in slave mode. if receive is enabled, by setting bit cren, prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr register will transfer the data to the rcreg register and if enable bit rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector (0004h). steps to follow when setting up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, then set enable bit rcie. 3. if 9-bit reception is desired, then set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is com- plete and an interrupt will be generated, if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 111 table 9-10 registers associated with synchronous slave transmission table 9-11 registers associated with synchronous slave reception address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19h txreg usart transmit register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous slave transmission. note 1: bits pspie and pspif are reserved on the 28-pin devices, always maintain these bits clear. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 18h rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 1ah rcreg usart receive register 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 98h txsta csrc tx9 txen sync brgh trmt tx9d 0000 -010 0000 -010 99h spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented read as '0'. shaded cells are not used for synchronous slave reception. note 1: bits pspie and pspif are reserved on the 28-pin devices, always maintain these bits clear.
pic16c77x ds30275a-page 112 advance information ? 1999 microchip technology inc. notes:
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 113 10.0 voltage reference module and low-voltage detect the voltage reference module provides reference volt- ages for the brown-out reset circuitry, the low-voltage detect circuitry and the a/d converter. the source for the reference voltages comes from the bandgap reference circuit. the bandgap circuit is ener- gized anytime the reference voltage is required by the other sub-modules, and is powered down when not in use. the control registers for this module are lvdcon and refcon, as shown in figure 10-1 and figure 10-2. figure 10-1: lvdcon: low-voltage detect control register u-0 u-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 bgst lvden lv3 lv2 lv1 lv0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n =value at por reset bit7 bit0 bit 7-6: unimplemented : read as '0' bit 5: bgst : bandgap stable status flag bit 1 = indicates that the bandgap voltage is stable, and lvd interrupt is reliable 0 = indicates that the bandgap voltage is not stable, and lvd interrupt should not be enabled bit 4: lvden : low-voltage detect power enable bit 1 = enables lvd, powers up bandgap circuit and reference generator 0 = disables lvd, powers down bandgap circuit if unused by bor or vrh/vrl bit 3-0: lv3:lv0 : low voltage detection limit bits (1) 1111 = external analog input is used 1110 = 4.5v 1101 = 4.2v 1100 = 4.0v 1011 = 3.8v 1010 = 3.6v 1001 = 3.5v 1000 = 3.3v 0111 = 3.0v 0110 = 2.8v 0101 = 2.7v 0100 = 2.5v note 1: these are the minimum trip points for the lvd, see table 15-3 for the trip point tolerances. selection of an unused setting may result in an inadvertant interrupt.
pic16c77x ds30275a-page 114 advance information ? 1999 microchip technology inc. figure 10-2: refcon: voltage reference control register 10.1 bandgap voltage reference the bandgap module generates a stable voltage refer- ence of 1.22v over a range of temperatures and device supply voltages. this module is enabled anytime any of the following are enabled: ? brown-out reset ? low-voltage detect ? either of the internal analog references (vrh, vrl) whenever the above are all disabled, the bandgap module is disabled and draws no current. 10.2 internal v ref for a/d converter the bandgap output voltage is used to generate two stable references for the a/d converter module. these references are enabled in software to provide the user with the means to turn them on and off in order to min- imize current consumption. each reference can be indi- vidually enabled. the 4.096v reference (vrh) is enabled with control bit vrhen (refcon<7>). when this bit is set, the gain amplifier is enabled. after a specified start-up time a stable reference of 4.096v is generated and can be used by the a/d converter as the vrh input. the 2.048v reference (vrl) is enabled by setting con- trol bit vrlen (refcon<6>). when this bit is set, the gain amplifier is enabled. after a specified start up time a stable reference of 2.048v is generated and can be used by the a/d converter as the vrl input. each voltage reference can source/sink up to 5 ma of current. each reference, if enabled, can be presented on an external pin by setting the vrhoen (high reference output enable) or vrloen (low reference output enable) control bit. if the reference is not enabled, the vrhoen and vrloen bits will have no effect on the corresponding pin. the device specific pin can then be used as general purpose i/o. r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 vrhen vrlen vrhoen vrloen r = readable bit w = writable bit u = unimplemented bit, read as 0 - n =value at por reset bit7 bit0 bit 7: vrhen : voltage reference high enable bit (vrh = 4.096v) 1 = enabled, powers up reference generator 0 = disabled, powers down reference generator if unused by lvd, bor, or vrl bit 6: vrlen : voltage reference low enable bit (vrl = 2.048v) 1 = enabled, powers up reference generator 0 = disabled, powers down reference generator if unused by lvd, bor, or vrh bit 5: vrhoen : high voltage reference output enable bit 1 = enabled, vrh analog reference is presented on ra3 if enabled (vrhen = 1) 0 = disabled, analog reference is used internally only bit 4: vrloen : low voltage reference output enable bit 1 = enabled, vrl analog reference is presented on ra2 if enabled (vrlen = 1) 0 = disabled, analog reference is used internally only bit 3-0: unimplemented : read as '0 note: if vrh or vrl is enabled and the other ref- erence (vrl or vrh), the bor, and the lvd modules are not enabled, the band- gap will require a start-up time of no more than 50 m s before the bandgap reference is stable. before using the internal vrh or vrl reference, ensure that the bandgap reference voltage is stable by monitoring the bgst bit in the lvdcon register. the voltage references will not be reliable until the bandgap is stable as shown by bgst being set.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 115 10.3 low-voltage detect (lvd) this module is used to generate an interrupt when the supply voltage falls below a specified trip voltage. this module operates completely under software control. this allows a user to power the module on and off to periodically monitor the supply voltage, and thus minimize total current consumption. figure 10-3: block diagram of lvd and voltage reference circuit the lvd module is enabled by setting the lvden bit in the lvdcon register. the trip point voltage is the minimum supply voltage level at which the device can operate before the lvd module asserts an interrupt. when the supply voltage is equal to or less than the trip point, the module will generate an interrupt signal set- ting interrupt flag bit lvdif. if interrupt enable bit lvdie was set, then an interrupt is generated. the lvd inter- rupt can wake the device from sleep. the "trip point" voltage is software programmable to any one of 16 val- ues, five of which are reserved (see figure 10-1). the trip point is selected by programming the lv3:lv0 bits (lvdcon<3:0>). once the lv bits have been programmed for the speci- fied trip voltage, the low-voltage detect circuitry is then enabled by setting the lvden (lvdcon<4>) bit. if the bandgap reference voltage is previously unused by either the brown-out circuitry or the voltage refer- ence circuitry, then the bandgap circuit requires a time to start-up and become stable before a low voltage con- dition can be reliably detected. the low-voltage inter- rupt flag is prevented from being set until the bandgap has reached a stable reference voltage. when the bandgap is stable the bgst (lvdcon<5>) bit is set indicating that the low-voltage interrupt flag bit is released to be set if v dd is equal to or less than the lvd trip point. 10.3.1 external analog voltage input the lvd module has an additional feature that allows the user to supply the trip voltage to the module from an external source. this mode is enabled when lv3:lv0 = 1111 . when these bits are set the compar- ator input is multiplexed from an external input pin (rb3/an9/lvdin. v dd lvd 16 to 1 mux bgap a/d ref = 4.096v a/d ref = 2.048v en lvdcon refcon boden lvden vrxen rb3/an9/lvdin v dd note: the lvdif bit can not be cleared until the supply voltage rises above the lvd trip point. if interrupts are enabled, clear the lvdie bit once the first lvd interrupt occurs to prevent reentering the interrupt service routine immediately after exiting the isr.
pic16c77x ds30275a-page 116 advance information ? 1999 microchip technology inc. notes:
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 117 11.0 analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has six inputs for the pic16c773 and ten for the pic16c774. the analog-to-digital converter (a/d) allows conver- sion of an analog input signal to a corresponding 12-bit digital number. the a/d module has up to 10 analog inputs, which are multiplexed into one sample and hold. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. the analog reference volt- ages are software selectable to either the devices analog positive and negative supply voltages (av dd /av ss ), the voltage level on the v ref + and v ref - pins, or internal voltage references if available (vrh, vrl). the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to operate in sleep, the a/d conversion clock must be derived from the a/ds internal rc oscillator. the a/d module has four registers. these registers are: ? a/d result register low adresl ? a/d result register high adresh ? a/d control register 0 (adcon0) ? a/d control register 1 (adcon1) a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion is aborted. 11.1 control registers the adcon0 register, shown in figure 11-1 , controls the operation of the a/d module. the adcon1 regis- ter, shown in figure 11-2 , configures the functions of the port pins, the voltage reference configuration and the result format. the port pins can be configured as analog inputs or as digital i/o. the combination of the adresh and adresl regis- ters contain the result of the a/d conversion. the reg- ister pair is referred to as the adres register. when the a/d conversion is complete, the result is loaded into adres, the go/done bit (adcon0<2>) is cleared, and the a/d interrupt flag adif is set. the block diagram of the a/d module is shown in figure 11-3 . figure 11-1: adcon0 register (address 1fh). r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs1 adcs0 chs2 chs1 chs0 go/done chs3 adon r = readable bit w = writable bit - n = value at por reset bit7 bit 0 bit 7:6 adcs1:adcs0: a/d conversion clock select bits 00 = fosc/2 01 = fosc/8 10 = fosc/32 11 = f rc (clock derived from an rc oscillator = 1 mhz max) bit 5:3,1 chs3:chs0: analog channel select bits 0000 = channel 00 (an0) 0001 = channel 01 (an1) 0010 = channel 02 (an2) 0011 = channel 03 (an3) 0100 = channel 04 (an4) (reserved on 28-pin devices, do not use) 0101 = channel 05 (an5) (reserved on 28-pin devices, do not use) 0110 = channel 06 (an6) (reserved on 28-pin devices, do not use) 0111 = channel 07 (an7) (reserved on 28-pin devices, do not use) 1000 = channel 08 (an8) 1001 = channel 09 (an9) 1010, 1011, 1100, 1101, 1110,1111 are reserved, do not select. bit 2: go/done : a/d conversion status bit 1 = a/d conversion cycle in progress. setting this bit starts an a/d conversion cycle. this bit is automatically cleared by hardware when the a/d conversion has completed. 0 = a/d conversion completed/not in progress bit 0: adon: a/d on bit 1 = a/d converter module is operating 0 = a/d converter is shutoff and consumes no operating current
pic16c77x ds30275a-page 118 advance information ? 1999 microchip technology inc. figure 11-2: adcon1 register (address 9fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm vcfg2 vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 r = readable bit w = writable bit u = unimplemented bit, read as 0 - n = value at por reset bit7 bit 0 bit 7: adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6:4 vcfg2:vcfg0: voltage reference configuration bits bit 3:0 pcfg3:pcfg0: a/d port configuration bits (1) note 1: selection of an unimplemented channel produces a result of 0xffffff. a/d v ref h a/d v ref l 000 a vdd a vss 001 external v ref + external v ref - 010 internal vrh internal vrl 011 external v ref +a vss 100 internal vrh a vss 101 a vdd external v ref - 110 a vdd internal vrl 111 internal vrl a vss an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 0000 aaaaaaaaaa 0001 aaaaaaaaaa 0010 aaaaaaaaaa 0011 aaaaaaaaaa 0100 aaaaaaaaaa 0101 aaaaaaaaaa 0110 daaaaaaaaa 0111 ddaaaaaaaa 1000 dddaaaaaaa 1001 dddd aaaaaa 1010 ddddd aaaaa 1011 dddddd aaaa 1100 dddddddaaa 1101 ddddddddaa 1110 ddddddddda 1111 dddddddddd a = analog input d= digital i/o
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 119 the value that is in the adresh and adresl regis- ters are not modified for a power-on reset. the adresh and adresl registers will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 11.6 . after this acquisition time has elapsed the a/d conver- sion can be started. the following steps should be fol- lowed for doing an a/d conversion: 11.2 configuring the a/d module 11.3 configuring analog port pins the adcon1 and tris registers control the operation of the a/d port pins. the port pins that are desired as analog inputs must have their corresponding tris bit set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs3:chs0 bits and the tris bits. 11.3.1 configuring the reference voltages the vcfg bits in the adcon1 register configure the a/d module reference inputs. the reference high input can come from an internal reference (vrh) or (vrl), an external reference (v ref +), or a vdd . the low reference input can come from an internal refer- ence (vrl), an external reference (v ref -), or a vss . if an external reference is chosen for the reference high or reference low inputs, the port pin that multiplexes the incoming external references is configured as an analog input, regardless of the values contained in the a/d port configuration bits (pcfg3:pcfg0). after the a/d module has been configured as desired. and the analog input channels have their correspond- ing tris bits selected for port inputs, the selected channel must be acquired before conversion is started. the a/d conversion cycle can be initiated by setting the go/done bit. the a/d conversion begins, and lasts for 13t ad . the following steps should be fol- lowed for performing an a/d conversion: 1. configure the a/d module ? configure analog pins / voltage reference / and digital i/o (adcon1) ? select a/d input channel (adcon0) ? select a/d conversion clock (adcon0) ? turn on a/d module (adcon0) 2. configure a/d interrupt (if required) ? clear adif bit ? set adie bit ? set peie bit ? set gie bit 3. wait the required acquisition time (3t ad ) 4. start conversion ? set go/done bit (adcon0) 5. wait 13t ad until a/d conversion is complete, by either: ? polling for the go/done bit to be cleared or ? waiting for the a/d interrupt 6. read a/d result registers (adresh and adresl), clear adif if required. 7. for next conversion, go to step 1, step 2 or step 3 as required. clearing the go/done bit during a conversion will abort the current conversion. the adresh and adresl registers will be updated with the partially completed a/d conversion value. that is, the adresh and adresl registers will contain the value of the current incomplete conversion. note 1: when reading the porta or porte reg- ister, all pins configured as analog input channels will read as cleared (a low level). when reading the portb register, all pins configured as analog input channels will read as set (a high level). pins config- ured as digital inputs, will convert an ana- log input. analog levels on a digitally configured input will not affect the conver- sion accuracy. note 2: analog levels on any pin that is defined as a digital input (including the anx pins), may cause the input buffer to consume current that is out of the devices specifica- tion. note: do not set the adon bit and the go/done bit in the same instruction. doing so will cause the go/done bit to be automatically cleared.
pic16c77x ds30275a-page 120 advance information ? 1999 microchip technology inc. figure 11-3: a/d block diagram (input voltage) v ain v refh (reference voltage) av dd vcfg2:vcfg0 chs3:chs0 re2/an7 (1) re1/an6 (1) re0/an5 (1) ra5/an4 (1) ra3/an3/v ref +/vrh ra2/an2/v ref -/vrl ra1/an1 ra0/an0 a/d converter note 1: not available on 28-pin devices. v refl (reference voltage) av ss vcfg2:vcfg0 rb2/an8 rb3/an9 vrh vrl vrl
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 121 11.4 selecting the a/d conversion clock the a/d conversion cycle requires 13t ad : 1 t ad for set- tling time, and 12 t ad for conversion. the source of the a/d conversion clock is software selected. the four possible options for t ad are: ?2 t osc ?8 t osc ?32 t osc ? internal rc oscillator note that these options are the same as those of the 8-bit a/d. for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 m s. ta bl e 1 1 - 1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. the adif bit is set on the rising edge of the 14th t ad . the go/done bit is cleared on the falling edge of the 14th t ad . table 11-1 t ad vs. device operating frequencies 11.5 a/d conversions figure 11-5 shows an example that performs an a/d conversion. the port pins are configured as analog inputs. the analog reference v ref + is the device av dd and the analog reference v ref - is the device av ss . the a/d interrupt is enabled, and the a/d conversion clock is t rc . the conversion is performed on the an0 chan- nel. figure 11-4: performing an a/d conversion bcf pir1, adif ;clear a/d int flag bsf status, rp0 ;select page 1 clrf adcon1 ;configure a/d inputs bsf pie1, adie ;enable a/d interrupt bcf status, rp0 ;select page 0 movlw 0xc1 ;rc clock, a/d is on, ;ch 0 is selected movwf adcon0 ; bsf intcon, peie ;enable peripheral bsf intcon, gie ;enable all interrupts ; ; ensure that the required sampling time for the ; selected input channel has lapsed. then the ; conversion may be started. bsf adcon0, go ;start a/d conversion : ;the adif bit will be ;set and the go/done bit : ;cleared upon completion- ;of the a/d conversion. ad clock source (t ad ) device frequency operation adcs<1:0> 20 mhz 5 mhz 4 mhz 1.25 mhz 2 t osc 00 100 ns (2) 400 ns (2) 500 ns (2) 1.6 m s 8 t osc 01 800 ns (2) 1.6 m s2.0 m s6.4 m s 32 t osc 10 1.6 m s6.4 m s 8.0 m s (3) 24 m s (3) rc 11 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) 2 - 6 m s (1,4) note 1: the rc source has a typical t ad time of 4 m s for v dd > 3.0v. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when the device frequency is greater than 1 mhz, the rc a/d conversion clock source is only recommended if the conver- sion will be performed during sleep.
pic16c77x ds30275a-page 122 advance information ? 1999 microchip technology inc. figure 11-5: flowchart of a/d operation sample adon = 0 adon = 0? go = 0? a/d clock go = 0 adif = 0 abort conversion sleep power down a/d wait 2 t ad wake-up ye s no ye s no no ye s finish conversion go = 0 adif = 1 sleep no ye s finish conversion go = 0 adif = 1 wait 2 t ad stay in sleep selected channel = rc? instruction? sleep no ye s instruction? start of a/d conversion delayed 1 instruction cycle from sleep? powerdown a/d ye s no wait 2 t ad finish conversion go = 0 adif = 1
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 123 11.6 a/d sample requirements 11.6.1 recommended source impedance the maximum recommended impedance for ana- log sources is 2.5 k w . this value is calculated based on the maximum leakage current of the input pin. the leakage current is 100 na max., and the analog input voltage cannot be vary by more than 1/4 lsb or 250 mv due to leakage. this places a requirement on the input impedance of 250 m v/100 na = 2.5 k w . 11.6.2 sampling time calculation for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 11-8 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 11-8 . the maximum recom- mended impedance for analog sources is 2.5 k w . after the analog input channel is selected (changed) this sampling must be done before the conversion can be started. to calculate the minimum sampling time, equation 11-6 may be used. this equation assumes that 1/4 lsb error is used (16384 steps for the a/d). the 1/4 lsb error is the maximum error allowed for the a/d to meet its specified resolution. the c hold is assumed to be 25 pf for the 12-bit a/d. figure 11-6: a/d sampling time equation v hold =(v ref - v ref /16384) = (v ref ) ? (1 -e (-t c /c (r ic +r ss + r s ) ) v ref (1 - 1/16384) = v ref ? (1 -e (-t c /c (r ic +r ss + r s ) ) t c = -c hold (1k w + r ss + r s ) in (1/16384) figure 11-7 shows the calculation of the minimum time required to charge c hold . this calculation is based on the following system assumptions: c hold = 25 pf r s = 2.5 k w 1/4 lsb error v dd = 5v ? r ss = 10 k w (worst case) temp (system max.) = 50 c note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 2.5 k w . this is required to meet the pin leakage specifi- cation. 4: after a conversion has completed, 2 t ad time must be waited before sampling can begin again. during this time the holding capacitor is not connected to the selected a/d input channel.
pic16c77x ds30275a-page 124 advance information ? 1999 microchip technology inc. figure 11-7: calculating the minimum required sample time t acq = amplifier settling time + holding capacitor charging time +temperature coefficient ? t acq =5 m s + t c + [(temp - 25 c)(0.05 m s/ c)] ? t c = + holding capacitor charging time t c =(c hold ) (r ic + r ss + r s ) in (1/16384) t c = -25 pf (1 k w +10 k w + 2.5 k w ) in (1/16384) t c = -25 pf (13.5 k w ) in (1/16384) t c = -0.338 (-9.704) m s t c =3.3 m s t acq =5 m s + 3.3 m s + [(50 c - 25 c)(0.05 m s / c)] t acq =8.3 m s + 1.25 m s t acq = 9.55 m s ? the temperature coefficient is only required for temperatures > 25 c. figure 11-8: analog input model c pin va rs port pin 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 25 pf v ss 6v sampling switch 5v 4v 3v 2v 567891011 ( k w ) v dd 100 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 125 11.7 use of the ccp trigger an a/d conversion can be started by the special event trigger of the ccp module. this requires that the ccpnm<3:0> bits be programmed as 1011b and that the a/d module is enabled (adon is set). when the trigger occurs, the go/done bit will be set on q2 to start the a/d conversion and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d conversion cycle, with minimal software overhead (moving the adresh and adresl to the desired location). the appropriate analog input chan- nel must be selected before the special event trigger sets the go/done bit (starts a conversion cycle). if the a/d module is not enabled (adon is cleared), then the special event trigger will be ignored by the a/d module, but will still reset the timer1 counter. 11.8 effects of a reset a device reset forces all registers to their reset state. this forces the a/d module to be turned off, and any conversion is aborted. the value that is in the adresh and adresl registers are not modified. the adresh and adresl registers will contain unknown data after a power-on reset. 11.9 faster conversion - lower resolution trade-off not all applications require a result with 12-bits of res- olution, but may instead require a faster conversion time. the a/d module allows users to make the trade-off of conversion speed to resolution. regard- less of the resolution required, the acquisition time is the same. to speed up the conversion, the a/d mod- ule may be halted by clearing the go/done bit after the desired number of bits in the result have been con- verted. once the go/done bit has been cleared, all of the remaining a/d result bits are 0. the equation to determine the time before the go/done bit can be switched is as follows: conversion time = n?t ad + 1t ad where: n = number of bits of resolution required, and 1t ad is the amplifier settling time. since t ad is based from the device oscillator, the user must use some method (a timer, software loop, etc.) to determine when the a/d go/done bit may be cleared. table 11-2 shows a comparison of time required for a conversion with 4-bits of resolution, ver- sus the normal 12-bit resolution conversion. the example is for devices operating at 20 mhz. the a/d clock is programmed for 32 t osc . table 11-2 4-bit vs. 12-bit conversion times freq. (mhz) resolution 4-bit 12-bit tosc 20 50 ns 50 ns t ad = 32 tosc 20 1.6 m s1.6 m s 1t ad +n?t ad 20 8 m s20.8 m s
pic16c77x ds30275a-page 126 advance information ? 1999 microchip technology inc. 11.10 a/d operation during sleep the a/d module can operate during sleep mode. this requires that the a/d clock source be configured for rc (adcs1:adcs0 = 11b ). with the rc clock source selected, when the go/done bit is set the a/d module waits one instruction cycle before starting the conver- sion cycle. this allows the sleep instruction to be exe- cuted, which eliminates all digital switching noise during the sample and conversion. when the conver- sion cycle is completed the go/done bit is cleared, and the result loaded into the adresh and adresl registers. if the a/d interrupt is enabled, the device will wake-up from sleep. if the a/d interrupt is not enabled, the a/d module will then be turned off, although the adon bit will remain set. when the a/d clock source is another clock option (not rc), a sleep instruction causes the present conver- sion to be aborted and the a/d module is turned off, though the adon bit will remain set. turning off the a/d places the a/d module in its lowest current consumption state. 11.11 connection considerations since the analog inputs employ esd protection, they have diodes to v dd and v ss . this requires that the analog input must be between v dd and v ss . if the input voltage exceeds this range by greater than 0.3v (either direction), one of the diodes becomes forward biased and it may damage the device if the input current spec- ification is exceeded. an external rc filter is sometimes added for anti-alias- ing of the input signal. the r component should be selected to ensure that the total source impedance is kept under the 2.5 k w recommended specification. any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. table 11-3 summary of a/d registers note: for the a/d module to operate in sleep , the a/d clock source must be configured to rc (adcs1:adcs0 = 11b ). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh,8bh, 10bh,18bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 1eh adresh a/d high byte result register xxxx xxxx uuuu uuuu 9eh adresl a/d low byte result register xxxx xxxx uuuu uuuu 9bh refcon vrhen vrlen vrhoen vrloen 0000 ---- 0000 ---- 1fh adcon0 adcs1 adcs0 chs2 chs1 chs0 go/done chs3 adon 0000 0000 0000 0000 9fh adcon1 adfm vcfg2 vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 0000 0000 0000 0000 05h porta porta5 (2) porta data latch when written: porta<4:0> pins when read --0x 0000 --0u 0000 06h portb portb data latch when written: portb pins when read xxxx 11xx uuuu 11uu 09h (2) porte re2 re1 re0 ---- -000 ---- -000 85h trisa bit5 (2) porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 89h (2) trise ibf obf ibov pspmode porte data direction bits 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used for a/d conversion. note 1: bits pspie and pspif are reserved on the 28-pin devices, always maintain these bits clear. 2: these bits/registers are not implemented on the 28-pin devices, read as '0'.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 127 12.0 special features of the cpu these picmicro devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protec- tion. these are: ? oscillator selection ? reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? low-voltage detection ? sleep ? code protection ? id locations ? in-circuit serial programming these devices have a watchdog timer which can be shut off only through configuration bits. it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 72 ms (nominal) on power-up type resets only (por, bor), designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset cir- cuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up, or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options. additional information on special features is available in the picmicro? mid-range reference manual, (ds33023). 12.1 configuration bits the configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. these bits are mapped in pro- gram memory location 2007h. the user will note that address 2007h is beyond the user program memory space. in fact, it belongs to the special test/configuration memory space (2000h - 3fffh), which can be accessed only during program- ming. some of the core features provided may not be neces- sary to each application that a device may be used for. the configuration word bits allow these features to be configured/enabled/disabled as necessary. these fea- tures include code protection, brown-out reset and its trippoint, the power-up timer, the watchdog timer and the devices oscillator mode. as can be seen in figure 12-1 , some additional configuration word bits have been provided for brown-out reset trippoint selec- tion.
pic16c77x ds30275a-page 128 advance information ? 1999 microchip technology inc. figure 12-1: configuration word 12.2 oscillator configurations 12.2.1 oscillator types the pic16c77x can be operated in four different oscil- lator modes. the user can program two configuration bits (fosc1 and fosc0) to select one of these four modes: ? lp low power crystal ? xt crystal/resonator ? hs high speed crystal/resonator ? rc resistor/capacitor 12.2.2 crystal oscillator/ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation ( figure 12-2 ). the pic16c77x oscillator design requires the use of a par- allel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifica- tions. a difference from the other mid-range devices may be noted in that the device can be driven from an external clock only when configured in hs mode ( figure 12-3 ). cp1 cp0 borv1 borv0 cp1 cp0 - boden cp1 cp0 pwrte wdte fosc1 fosc0 register: config address 2007h bit13 12 11 10 9 8 7 6 5 4 3 2 1 bit0 bit 13-12: cp1:cp0: code protection bits (2) bit 9-8: 11 = program memory code protection off bit 5-4: 10 = 0800h-0fffh code protected 01 = 0400h-0fffh code protected 00 = 0000h-0fffh code protected bit 11-10: borv1:borv0 : brown-out reset voltage bits (3) 11 = v bor set to 2.5v 10 = v bor set to 2.7v 01 = v bor set to 4.2v 00 = v bor set to 4.5v bit 7: unimplemented , read as '1' bit 6: boden : brown-out reset enable bit (1) 1 = brown-out reset enabled 0 = brown-out reset disabled bit 3: pwrte : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enabling brown-out reset automatically enables the power-up timer (pwrt) regardless of the value of bit pwrte . ensure the power-up timer is enabled anytime brown-out reset is enabled. 2: all of the cp1:cp0 pairs have to be given the same value to enable the code protection scheme listed. 3: these are the minimum trip points for the bor, see table 15-4 for the trip point tolerances. selection of an unused setting may result in an inadvertant interrupt.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 129 figure 12-2: crystal/ceramic resonator operation (hs, xt or lp osc configuration) figure 12-3: external clock input operation (hs osc configuration) table 12-1 ceramic resonators table 12-2 capacitor selection for crystal oscillator ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf 10 - 68 pf 10 - 22 pf these values are for design guidance only. see notes at bottom of page. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors. note1: see table 12-1 and ta bl e 1 2 - 2 for recom- mended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen. c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to logic pic16c77x rs (2) internal osc1 osc2 open clock from ext. system pic16c77x osc type crystal freq cap. range c1 cap. range c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15 pf 15 pf 4 mhz 15 pf 15 pf hs 4 mhz 15 pf 15 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf these values are for design guidance only. see notes at bottom of page. crystals used 32 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1 mhz ecs ecs-10-13-1 50 ppm 4 mhz ecs ecs-40-20-1 50 ppm 8 mhz epson ca-301 8.000m-c 30 ppm 20 mhz epson ca-301 20.000m-c 30 ppm note 1: recommended values of c1 and c2 are identical to the ranges tested ( ta bl e 1 2 - 1 ). 2: higher capacitance increases the stability of oscillator but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. 4: rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level specification.
pic16c77x ds30275a-page 130 advance information ? 1999 microchip technology inc. 12.2.3 rc oscillator for timing insensitive applications the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. these factors and the variation due to tol- erances of external r and c components used need to be taken into account for each application. figure 12-4 shows how the r/c combination is connected to the pic16c77x. figure 12-4: rc oscillator mode osc2/clkout cext rext pic16c77x osc1 fosc/4 internal clock v dd v ss
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 131 12.3 reset the pic16c77x devices have several different resets. these resets are grouped into two classifications; power-up and non-power-up. the power-up type resets are the power-on and brown-out resets which assume the device v dd was below its normal operating range for the devices configuration. the non-power up type resets assume normal operating limits were main- tained before/during and after the reset. ? power-on reset (por) ? brown-out reset (bor) ?mclr reset during normal operation ?mclr reset during sleep ? wdt reset (during normal operation) some registers are not affected in any reset condition. their status is unknown on a power-up reset and unchanged in any other reset. most other registers are placed into an initialized state upon reset, however they are not affected by a wdt reset during sleep because this is considered a wdt wakeup, which is viewed as the resumption of normal operation. several status bits have been provided to indicate which reset occurred (see ta bl e 1 2 - 4 ). see ta bl e 1 2 - 6 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 12-5 . these devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. figure 12-5: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt module v dd rise detect ost/pwrt on-chip rc osc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clkin pin. brown-out reset boden (1)
pic16c77x ds30275a-page 132 advance information ? 1999 microchip technology inc. 12.4 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.5v - 2.1v). to take advantage of the por, just tie the mclr pin directly (or through a resistor) to v dd . this will elimi- nate external rc components usually needed to create a power-on reset. a maximum rise time for v dd is specified. see electrical specifications for details. for a slow rise time, see figure 12-6 . two delay timers have been provided which hold the device in reset after a por (dependant upon device configuration) so that all operational parameters have been met prior to releasing to device to resume/begin normal operation. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure oper- ation. if these conditions are not met, the device must be held in reset until the operating conditions are met. brown-out reset may be used to meet the startup con- ditions, or if necessary an external por circuit may be implemented to delay end of reset for as long as needed. figure 12-6: external power-on reset circuit (for slow v dd power-up) 12.5 power-up timer (pwrt) the power-up timer provides a fixed 72 ms nominal time-out on power-up type resets only. for a por, the pwrt is invoked when the por pulse is generated. for a bor, the pwrt is invoked when the device exits the reset condition (v dd rises above bor trippoint). the power-up timer operates on an internal rc oscil- lator. the chip is kept in reset as long as the pwrt is active. the pwrts time delay is designed to allow v dd to rise to an acceptable level. a configuration bit is pro- vided to enable/disable the pwrt for the por only. for a bor the pwrt is always available regardless of the configuration bit setting. the power-up time delay will vary from chip to chip due to v dd , temperature, and process variation. see dc parameters for details. 12.6 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over. this ensures that the crystal oscil- lator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp and hs modes and only on a power-up type reset or a wake-up from sleep. 12.7 brown-out reset (bor) the brown-out reset module is used to generate a reset when the supply voltage falls below a specified trip voltage. the trip voltage is configurable to any one of four voltages provided by the borv1:borv0 config- uration word bits. configuration bit, boden, can disable (if clear/pro- grammed) or enable (if set) the brown-out reset cir- cuitry. if v dd falls below the specified trippoint for greater than parameter #35 in the electrical specifica- tions section, the brown-out situation will reset the chip. a reset may not occur if v dd falls below the trippoint for less than parameter #35. the chip will remain in brown- out reset until v dd rises above bv dd . the power-up timer will be invoked at that point and will keep the chip in reset an additional 72 ms. if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be re-initialized. once v dd rises above bv dd , the power-up timer will again begin a 72 ms time delay. even though the pwrt is always enabled when brown-out is enabled, the pwrt configuration word bit should be cleared (enabled) when brown-out is enabled. note 1: external power-on reset circuit is required only if v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k w is recommended to make sure that voltage drop across r does not violate the devices electrical specification. 3: r1 = 100 w to 1 k w will limit any current flowing into mclr from external capacitor c in the event of mclr/ v pp pin break- down due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic16c77x
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 133 12.8 time-out sequence on power-up the time-out sequence is as follows: first pwrt time-out is invoked by the por pulse. when the pwrt delay expires the oscillator start-up timer is activated. the total time-out will vary based on oscilla- tor configuration and the status of the pwrt. for exam- ple, in rc mode with the pwrt disabled, there will be no time-out at all. figure 12-7 , figure 12-8 , figure 12- 9 and figure 12-10 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. then bringing mclr high will begin execution immediately ( figure 12-9 ). this is useful for testing purposes or to synchronize more than one picmicro microcontroller operating in parallel. ta bl e 1 2 - 5 shows the reset conditions for some special function registers, while ta bl e 1 2 - 6 shows the reset conditions for all the registers. 12.9 power control/status register (pcon) the power control/status register, pcon has two sta- tus bits that provide indication of which power-up type reset occurred. bit0 is brown-out reset status bit, bor . bit bor is set on a power-on reset. it must then be set by the user and checked on subsequent resets to see if bit bor cleared, indicating a bor occurred. however, if the brown-out circuitry is disabled, the bor bit is a "dont care" bit and is considered unknown upon a por. bit1 is por (power-on reset status bit). it is cleared on a power-on reset and unaffected otherwise. the user must set this bit following a power-on reset. table 12-3 time-out in various situations table 12-4 status bits and their significance table 12-5 reset condition for special registers oscillator configuration power-up brown-out wake-up from sleep pwrte = 0 pwrte = 1 xt, hs, lp 72 ms + 1024t osc 1024t osc 72 ms + 1024t osc 1024t osc rc 72 ms 72 ms por bor to pd 0111 power-on reset 0x0x illegal, to is set on por 0xx0 illegal, pd is set on por 1011 brown-out reset 1101 wdt reset 1100 wdt wake-up 11uu mclr reset during normal operation 1110 mclr reset during sleep or interrupt wake-up from sleep condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --01 mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 1uuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 0001 1uuu ---- --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. note 1: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h).
pic16c77x ds30275a-page 134 advance information ? 1999 microchip technology inc. table 12-6 initialization conditions for all registers register devices power-on reset, brown-out reset mclr resets wdt reset wake-up via wdt or interrupt w 773 774 xxxx xxxx uuuu uuuu uuuu uuuu indf 773 774 n/a n/a n/a tmr0 773 774 xxxx xxxx uuuu uuuu uuuu uuuu pcl 773 774 0000h 0000h pc + 1 (2) status 773 774 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 773 774 xxxx xxxx uuuu uuuu uuuu uuuu porta 773 774 --0x 0000 --0u 0000 --uu uuuu portb 773 774 xxxx 11xx uuuu 11uu uuuu uuuu portc 773 774 xxxx xxxx uuuu uuuu uuuu uuuu portd 773 774 xxxx xxxx uuuu uuuu uuuu uuuu porte 773 774 ---- -000 ---- -000 ---- -uuu pclath 773 774 ---0 0000 ---0 0000 ---u uuuu intcon 773 774 0000 000x 0000 000u uuuu uuuu (1) pir1 773 774 r000 0000 r000 0000 ruuu uuuu (1) 773 774 0000 0000 0000 0000 uuuu uuuu (1) pir2 773 774 0--- 0--0 0--- 0--0 u--- u--u (1) tmr1l 773 774 xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 773 774 xxxx xxxx uuuu uuuu uuuu uuuu t1con 773 774 --00 0000 --uu uuuu --uu uuuu tmr2 773 774 0000 0000 0000 0000 uuuu uuuu t2con 773 774 -000 0000 -000 0000 -uuu uuuu sspbuf 773 774 xxxx xxxx uuuu uuuu uuuu uuuu sspcon 773 774 0000 0000 0000 0000 uuuu uuuu ccpr1l 773 774 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h 773 774 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 773 774 --00 0000 --00 0000 --uu uuuu rcsta 773 774 0000 000x 0000 000x uuuu uuuu txreg 773 774 0000 0000 0000 0000 uuuu uuuu rcreg 773 774 0000 0000 0000 0000 uuuu uuuu ccpr2l 773 774 xxxx xxxx uuuu uuuu uuuu uuuu ccpr2h 773 774 xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 773 774 --00 0000 --00 0000 --uu uuuu adresh 773 774 xxxx xxxx uuuu uuuu uuuu uuuu adcon0 773 774 0000 0000 0000 0000 uuuu uuuu option_reg 773 774 1111 1111 1111 1111 uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see ta bl e 1 2 - 5 for reset value for specific condition.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 135 figure 12-7: time-out sequence on power-up (mclr tied to v dd ) trisa 773 774 ---1 1111 ---1 1111 ---u uuuu 773 774 --11 1111 --11 1111 --uu uuuu trisb 773 774 1111 1111 1111 1111 uuuu uuuu trisc 773 774 1111 1111 1111 1111 uuuu uuuu trisd 773 774 1111 1111 1111 1111 uuuu uuuu trise 773 774 0000 -111 0000 -111 uuuu -uuu pie1 773 774 r000 0000 r000 0000 ruuu uuuu 773 774 0000 0000 0000 0000 uuuu uuuu pie2 773 774 0--- 0--0 0--- 0--0 u--- u--u pcon 773 774 ---- --qq ---- --uu ---- --uu pr2 773 774 1111 1111 1111 1111 1111 1111 sspadd 773 774 0000 0000 0000 0000 uuuu uuuu sspstat 773 774 0000 0000 0000 0000 uuuu uuuu txsta 773 774 0000 -010 0000 -010 uuuu -uuu spbrg 773 774 0000 0000 0000 0000 uuuu uuuu refcon 773 774 0000 ---- 0000 ---- uuuu ---- lvdcon 773 774 --00 0101 --00 0101 --uu uuuu adresl 773 774 xxxx xxxx uuuu uuuu uuuu uuuu adcon1 773 774 0000 000 0000 0000 uuuu uuuu table 12-6 initialization conditions for all registers (c ont.d) register devices power-on reset, brown-out reset mclr resets wdt reset wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition note 1: one or more bits in intcon, pir1 and/or pir2 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see ta bl e 1 2 - 5 for reset value for specific condition. t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset
pic16c77x ds30275a-page 136 advance information ? 1999 microchip technology inc. figure 12-8: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 12-9: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 12-10: slow rise time (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 137 12.10 interrupts the pic16c77x family has up to 14 sources of inter- rupt. the interrupt control register (intcon) records individual interrupt requests in flag bits. it also has indi- vidual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. when bit gie is enabled, and an interrupts flag bit and mask bit are set, the interrupt will vector immediately. individual interrupts can be dis- abled through their corresponding enable bits in vari- ous registers. individual interrupt bits are set regardless of the status of the gie bit. the gie bit is cleared on reset. the return from interrupt instruction, retfie , exits the interrupt routine as well as sets the gie bit, which re-enables interrupts. the rb0/int pin interrupt, the rb port change interrupt and the tmr0 overflow interrupt flags are contained in the intcon register. the peripheral interrupt flags are contained in the spe- cial function registers pir1 and pir2. the correspond- ing interrupt enable bits are contained in special function registers pie1 and pie2, and the peripheral interrupt enable bit is contained in special function reg- ister intcon. when an interrupt is responded to, the gie bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the pc is loaded with 0004h. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. for external interrupt events, such as the int pin or portb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs. the latency is the same for one or two cycle instructions. individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the gie bit figure 12-11: interrupt logic note: individual interrupt flag bits are set regard- less of the status of their corresponding mask bit or the gie bit. pspif pspie adif adie rcif rcie txif txie sspif sspie ccp1if ccp1ie tmr2if tmr2ie tmr1if tmr1ie t0if t0ie intf inte rbif rbie gie peie wake-up (if in sleep mode) interrupt to cpu ccp2ie ccp2if the following table shows which devices have which interrupts. device t0if intf rbif pspif adif rcif txif sspif ccp1if tmr2if tmr1if lvdif bclif ccp2if pic16c773 yes yes yes - yes yes yes yes yes yes yes yes yes yes pic16c774 yes yes yes yes yes yes yes yes yes yes yes yes yes yes lvdif lvdie bclie bclif
pic16c77x ds30275a-page 138 advance information ? 1999 microchip technology inc. 12.10.1 int interrupt external interrupt on rb0/int pin is edge triggered: either rising if bit intedg (option_reg<6>) is set, or falling, if the intedg bit is clear. when a valid edge appears on the rb0/int pin, flag bit intf (intcon<1>) is set. this interrupt can be disabled by clearing enable bit inte (intcon<4>). flag bit intf must be cleared in software in the interrupt service rou- tine before re-enabling this interrupt. the int interrupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of global inter- rupt enable bit gie decides whether or not the proces- sor branches to the interrupt vector following wake-up. see section 12.13 for details on sleep mode. 12.10.2 tmr0 interrupt an overflow (ffh ? 00h) in the tmr0 register will set flag bit t0if (intcon<2>). the interrupt can be enabled/disabled by setting/clearing enable bit t0ie (intcon<5>). ( section 4.0 ) 12.10.3 portb intcon change an input change on portb<7:4> sets flag bit rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit rbie (intcon<4>). ( section 3.2 ) 12.11 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt, i.e., w register and status register. this will have to be implemented in software. example 12-1 stores and restores the w and status registers. the register, w_temp, must be defined in each bank and must be defined at the same offset from the bank base address (i.e., if w_temp is defined at 0x20 in bank 0, it must also be defined at 0xa0 in bank 1). the example: a) stores the w register. b) stores the status register in bank 0. c) stores the pclath register. d) executes the interrupt service routine code (user-generated). e) restores the status register (and bank select bit). f) restores the w and pclath registers. example 12-1: saving status, w, and pclath registers in ram movwf w_temp ;copy w to temp register, could be bank one or zero swapf status,w ;swap status to be saved into w clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register movf pclath, w ;only required if using pages 1, 2 and/or 3 movwf pclath_temp ;save pclath into w clrf pclath ;page zero, regardless of current page bcf status, irp ;return to bank 0 movf fsr, w ;copy fsr to w movwf fsr_temp ;copy fsr from w to fsr_temp : :(isr) : movf pclath_temp, w ;restore pclath movwf pclath ;move w into pclath swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 139 12.12 watchdog timer (wdt) the watchdog timer is as a free running on-chip rc oscillator which does not require any external compo- nents. this rc oscillator is separate from the rc oscil- lator of the osc1/clkin pin. that means that the wdt will run, even if the clock on the osc1/clkin and osc2/clkout pins of the device has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the status register will be cleared upon a watchdog timer time-out. the wdt can be permanently disabled by clearing configuration bit wdte ( section 12.1 ). wdt time-out period values may be found in the elec- trical specifications section under parameter #31. val- ues for the wdt prescaler may be assigned using the option_reg register. . figure 12-12: watchdog timer block diagram figure 12-13: summary of watchdog timer registers note: the clrwdt and sleep instructions clear the wdt and the postscaler, if assigned to the wdt, and prevent it from timing out and generating a device reset condition. note: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h config. bits (1) boden (1) cp1 cp0 pwrte (1) wdte fosc1 fosc0 81h,181h option_reg rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see figure 12-1 for the full description of the configuration word bits. from tmr0 clock source ( figure 4-2 ) to t m r 0 ( section 4-2 ) postscaler wdt timer wdt enable bit 0 1 m u x psa 8 - to - 1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option_reg register. 8
pic16c77x ds30275a-page 140 advance information ? 1999 microchip technology inc. 12.13 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit (status<3>) is cleared, the to (status<4>) bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had, before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, place all i/o pins at either v dd , or v ss , ensure no external cir- cuitry is drawing current from the i/o pin, power-down the a/d, disable external clocks. pull all i/o pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on portb should be considered. the mclr pin must be at a logic high level (v ihmc ). 12.13.1 wake-up from sleep the device can wake up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change, or some peripheral interrupts. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and cause a "wake-up". the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the following peripheral interrupts can wake the device from sleep: 1. psp read or write. 2. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 3. ccp capture mode interrupt. 4. special event trigger (timer1 in asynchronous mode using an external clock). 5. ssp (start/stop) bit detect interrupt. 6. ssp transmit or receive in slave mode (spi/i 2 c). 7. usart rx or tx (synchronous slave mode). 8. a/d conversion (when a/d clock source is rc). 9. low-voltage detect. other peripherals cannot generate interrupts since dur- ing sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. 12.13.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as a nop. therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will imme- diately wake up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop. to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 141 figure 12-14: wake-up from sleep through interrupt 12.14 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 12.15 id locations four memory locations (2000h - 2003h) are designated as id locations where the user can store checksum or other code-identification numbers. these locations are not accessible during normal execution but are read- able and writable during program/verify. it is recom- mended that only the 4 least significant bits of the id location are used. for rom devices, these values are submitted along with the rom code. 12.16 in-circuit serial programming pic16cxxx microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firm- ware to be programmed. for complete details of serial programming, please refer to the in-circuit serial programming (icsp?) guide, (ds30277). q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout(4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = '1' assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = '0', execution will co ntinue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference. note: microchip does not recommend code pro- tecting windowed devices.
pic16c77x ds30275a-page 142 advance information ? 1999 microchip technology inc. notes:
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 143 13.0 instruction set summary each pic16cxxx instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction. the pic16cxx instruction set summary in ta b l e 1 3 - 2 lists byte-oriented , bit-ori- ented , and literal and control operations. ta bl e 1 3 - 1 shows the opcode field descriptions. for byte-oriented instructions, 'f' represents a file reg- ister designator and 'd' represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 13-1 opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop. one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 m s. ta bl e 1 3 - 2 lists the instructions recognized by the mpasm assembler. figure 13-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. figure 13-1: general format for instructions a description of each instruction is available in the picmicro? mid-range reference manual, (ds33023). field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in file register f. default is d = 1 pc program counter to time-out bit pd power-down bit note: to maintain upward compatibility with future pic16cxxx products, do not use the option and tris instructions. byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16c77x ds30275a-page 144 advance information ? 1999 microchip technology inc. table 13-2 pic16cxxx instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to , pd z to , pd c,dc,z z note 1: when an i/o register is modified as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop.
? 1999 microchip technology inc. ds30275a-page 145 pic16c77x 14.0 development support 14.1 development tools the picmicro a microcontrollers are supported with a full range of hardware and software development tools: ? mplab ? -ice real-time in-circuit emulator ? icepic ? low-cost pic16c5x and pic16cxxx in-circuit emulator ?pro mate a ii universal programmer ? picstart a plus entry-level prototype programmer ? simice ? picdem-1 low-cost demonstration board ? picdem-2 low-cost demonstration board ? picdem-3 low-cost demonstration board ? mpasm assembler ? mplab ? sim software simulator ? mplab-c17 (c compiler) ? fuzzy logic development system ( fuzzy tech a - mp) ?k ee l oq ? evaluation kits and programmer 14.2 mplab-ice: high performance universal in-circuit emulator with mplab ide the mplab-ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). mplab-ice is sup- plied with the mplab integrated development environ- ment (ide), which allows editing, make and download, and source debugging from a single envi- ronment. interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. the universal architecture of the mplab-ice allows expansion to support all new microchip micro- controllers. the mplab-ice emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive devel- opment tools. the pc compatible 386 (and higher) machine platform and microsoft windows a 3.x or windows 95 environment were chosen to best make these features available to you, the end user. mplab-ice is available in two versions. mplab-ice 1000 is a basic, low-cost emulator system with simple trace capabilities. it shares processor mod- ules with the mplab-ice 2000. this is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. both systems will operate across the entire operating speed reange of the picmicro mcu. 14.3 icepic: low-cost picmicro in-circuit emulator icepic is a low-cost in-circuit emulator solution for the microchip pic12cxxx, pic16c5x and pic16cxxx families of 8-bit otp microcontrollers. icepic is designed to operate on pc-compatible machines ranging from 386 through pentium ? based machines under windows 3.x, windows 95, or win- dows nt environment. icepic features real time, non- intrusive emulation. 14.4 pro mate ii: universal programmer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. pro mate ii is ce compliant. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand- alone mode the pro mate ii can read, verify or pro- gram pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx devices. it can also set configuration and code-protect bits in this mode. 14.5 picstart plus entry level development system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and efficient. picstart plus is not recommended for production programming. picstart plus supports all pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx devices with up to 40 pins. larger pin count devices such as the pic16c923, pic16c924 and pic17c756 may be sup- ported with an adapter socket. picstart plus is ce compliant.
pic16c77x ds30275a-page 146 ? 1999 microchip technology inc. 14.6 simice entry-level hardware simulator simice is an entry-level hardware development sys- tem designed to operate in a pc-based environment with microchips simulator mplab?-sim. both sim- ice and mplab-sim run under microchip technol- ogys mplab integrated development environment (ide) software. specifically, simice provides hardware simulation for microchips pic12c5xx, pic12ce5xx, and pic16c5x families of picmicro 8-bit microcontrol- lers. simice works in conjunction with mplab-sim to provide non-real-time i/o port emulation. simice enables a developer to run simulator code for driving the target system. in addition, the target system can provide input to the simulator code. this capability allows for simple and interactive debugging without having to manually generate mplab-sim stimulus files. simice is a valuable debugging tool for entry- level system development. 14.7 picdem-1 low-cost picmicro demonstration board the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample microcontrollers provided with the picdem-1 board, on a pro mate ii or picstart-plus programmer, and easily test firm- ware. the user can also connect the picdem-1 board to the mplab-ice emulator and download the firmware to the emulator for testing. additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 14.8 picdem-2 low-cost pic16cxx demonstration board the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-plus, and easily test firmware. the mplab-ice emulator may also be used with the picdem-2 board to test firmware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 14.9 picdem-3 low-cost pic16cxxx demonstration board the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test firmware. the mplab-ice emulator may also be used with the picdem-3 board to test firm- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the lcd signals.
? 1999 microchip technology inc. ds30275a-page 147 pic16c77x 14.10 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows based application which contains: ? a full featured editor ? three operating modes -editor -emulator - simulator ? a project manager ? customizable tool bar and key mapping ? a status bar with project information ? extensive on-line help mplab allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to picmicro tools (automatically updates all project information) ? debug using: - source files - absolute listing file the ability to use mplab with microchips simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 14.11 assembler (mpasm) the mpasm universal macro assembler is a pc- hosted symbolic assembler. it supports all microcon- troller series including the pic12c5xx, pic14000, pic16c5x, pic16cxxx, and pic17cxx families. mpasm offers full featured macro capabilities, condi- tional assembly, and several source and listing formats. it generates various object code formats to support microchip's development tools as well as third party programmers. mpasm allows full symbolic debugging from mplab- ice, microchips universal emulator system. mpasm has the following features to assist in develop- ing software for specific use applications. ? provides translation of assembler source code to object code for all microchip microcontrollers. ? macro assembly capability. ? produces all the files (object, listing, symbol, and special) required for symbolic debug with microchips emulator systems. ? supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the picmicro. directives are helpful in making the development of your assemble source code shorter and more maintainable. 14.12 software simulator (mplab-sim) the mplab-sim software simulator allows code development in a pc host environment. it allows the user to simulate the picmicro series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. mplab-sim fully supports symbolic debugging using mplab-c17 and mpasm. the software simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. 14.13 mplab-c17 compiler the mplab-c17 code development system is a complete ansi c compiler and integrated develop- ment environment for microchips pic17cxxx family of microcontrollers. the compiler provides powerful inte- gration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler pro- vides symbol information that is compatible with the mplab ide memory display. 14.14 fuzzy logic development system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic development tool is avail- able in two versions - a low cost introductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy tech-mp, edition for imple- menting more complex systems. both versions include microchips fuzzy lab ? demon- stration board for hands-on experience with fuzzy logic systems implementation. 14.15 seeval a evaluation and programming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can significantly reduce time-to-market and result in an optimized system.
pic16c77x ds30275a-page 148 ? 1999 microchip technology inc. 14.16 k ee l oq a evaluation and programming tools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
? 1999 microchip technology inc. ds30275a-page 149 pic16c77x table 14-1 development tools from microchip pic12c5xx pic14000 pic16c5x pic16cxxx pic16c6x pic16c7xx pic16c8x pic16c9xx pic17c4x pic17c7xx 24cxx 25cxx 93cxx hcs200 hcs300 hcs301 emulator products mplab ?-ice icepic ? low-cost in-circuit emulator software tools mplab ? integrated development environment mplab ? c17* compiler fuzzy tech a -mp explorer/edition fuzzy logic dev. tool total endurance ? software model programmer s picstart a plus low-cost universal dev. kit pro mate a ii universal programmer keeloq a programmer demo boards seeval a designers kit simice picdem-14a picdem-1 picdem-2 picdem-3 k ee l oq ? evaluation kit k ee l oq transponder kit
pic16c77x ds30275a-page 150 ? 1999 microchip technology inc. notes:
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 151 15.0 electrical characteristics absolute maximum ratings ? ambient temperature under bias................................................................................................. ............... . -55 to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr . and ra4).......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ............................................................................................................ -0.3 to +7.5v voltage on mclr with respect to v ss (note 2).................................................................................................0 to +8.5v voltage on ra4 with respect to vss ............................................................................................. .....................0 to +8.5v total power dissipation (note 1)............................................................................................... .................................1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta, portb, and porte (combined) (note 3)....................................................200 ma maximum current sourced by porta, portb, and porte (combined) (note 3) ..............................................200 ma maximum current sunk by portc and portd (combined) (note 3) ..................................................................20 0 ma maximum current sourced by portc and portd (combined) (note 3) .............................................................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - ? i oh } + ? {(v dd - v oh ) x i oh } + ? (v o l x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 w should be used when applying a low level to the mclr pin rather than pulling this pin directly to v ss . note 3: portd and porte are not implemented on the pic16c773. table 15-1 cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. osc pic16c773-04 pic16c774-04 pic16c773-20 pic16c774-20 pic16lc773-04 pic16lc774-04 jw devices rc v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 2.5v to 5.5v i dd : 3.8 ma max. at 3.0v i pd : 5 m a max. at 3v freq: 4 mhz max. v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. xt v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. at 5.5v i pd : 1.5 m a typ. at 4v freq: 4 mhz max. v dd : 2.5v to 5.5v i dd : 3.8 ma max. at 3.0v i pd : 5 m a max. at 3v freq: 4 mhz max. v dd : 4.0v to 5.5v i dd : 5 ma max. at 5.5v i pd : 16 m a max. at 4v freq: 4 mhz max. hs v dd : 4.5v to 5.5v v dd : 4.5v to 5.5v not tested for functionality v dd : 4.5v to 5.5v i dd : 13.5 ma typ. at 5.5v i dd : 20 ma max. at 5.5v i dd : 20 ma max. at 5.5v i pd : 1.5 m a typ. at 4.5v i pd :1.5 m a typ. at 4.5v i pd : 1.5 m a typ. at 4.5v freq: 4 mhz max. freq: 20 mhz max. freq: 20 mhz max. lp v dd : 4.0v to 5.5v i dd : 52.5 m a typ. at 32 khz, 4.0v i pd : 0.9 m a typ. at 4.0v freq: 200 khz max. not tested for functionality v dd : 2.5v to 5.5v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v freq: 200 khz max. v dd : 2.5v to 5.5v i dd : 48 m a max. at 32 khz, 3.0v i pd : 5.0 m a max. at 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max specifications. it is recommended that the user select the device type that ensures the specifications required.
pic16c77x ds30275a-page 152 advance information ? 1999 microchip technology inc. 15.1 dc characteristics: pic16c77x (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial and 0c t a +70c for commercial param no. characteristic sym min typ? max units conditions d001 d001a supply voltage v dd 4.0 4.5 5.5 5.5 v v xt, rc and lp osc configuration hs osc configuration d002* ram data retention voltage (note 1) v dr 1.5v d003 v dd start voltage to ensure internal power-on reset signal v por v ss v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 v/ms see section on power-on reset for details. pwrt enabled d010 d013 supply current (note 2) i dd 2.7 13.5 5 30 ma ma xt, rc osc configuration f osc = 4 mhz, v dd = 5.5v (note 4) hs osc configuration f osc = 20 mhz, v dd = 5.5v d020 d020a power-down current (note 3) i pd 1.5 1.5 16 19 m a m a v dd = 4.0v, -0 c to +70 c v dd = 4.0v, -40 c to +85 c module differential cur- rent (note 5) d021 watchdog timer d i wdt 6.020 m av dd = 4.0v d023* d023b* brown-out reset current (note 5) bandgap voltage generator d i bor d i bg 6 tbd 200 40 m a tbd m a m a bor enabled, v dd = 5.0v d025* timer1 oscillator d i t 1 osc 59 m av dd = 4.0v d026* a/d converter d i ad 300 m av dd = 5.5v, a/d on, not converting * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for rc osc configuration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: the d current is the additional current consumed when the peripheral is enabled. this current should be added to the base (i pd or i dd ) current. 6: the bandgap voltate reference provides 1.22v to the vrl, vrh, lvd and bor circuits. when calculating cur- rent consumption use the following formula: d i vrl + d i vrh + d i lvd + d i bor + d i bg . any of the d i vrl , d i vrh , d i lvd or d i bor can be 0.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 153 15.2 dc characteristics:pic16lc77x-04 (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial and 0c t a +70c for commercial param no. characteristic sym min typ? max units conditions d001 supply voltage v dd 2.5 5.5 v lp, xt, rc osc configuration (dc - 4 mhz) d002* ram data retention voltage (note 1) v dr 1.5 v d003 v dd start voltage to ensure internal power-on reset signal v por v ss v see section on power-on reset for details d004* v dd rise rate to ensure internal power-on reset signal s vdd 0.05 v/ms see section on power-on reset for details. pwrt enabled d010 d010a supply current (note 2) i dd 2.0 22.5 3.8 48 ma m a xt, rc osc configuration f osc = 4 mhz, v dd = 3.0v (note 4) lp osc configuration f osc = 32 khz, v dd = 3.0v, wdt dis- abled d020 d020a power-down current (note 3) i pd 0.9 0.9 5 5 m a m a v dd = 3.0v, 0 c to +70 c v dd = 3.0v, -40 c to +85 c module differential cur- rent (note5) d021 watchdog timer d i wdt 620 m av dd = 3.0v d023* brown-out reset current (note 5) d i bor tbd 200 m a bor enabled, v dd = 5.0v d025* timer1 oscillator d i t 1 osc 1.53 m av dd = 3.0v d026* a/d converter d i ad 300 m av dd = 5.5v, a/d on, not converting * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tristated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for rc osc configuration, current through rext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2rext (ma) with rext in kohm. 5: the d current is the additional current consumed when the peripheral is enabled. this current should be added to the base (i pd or i dd ) current.
pic16c77x ds30275a-page 154 advance information ? 1999 microchip technology inc. 15.3 dc characteristics: pic16c77x (commercial, industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial and 0c t a +70c for commercial operating voltage v dd range as described in dc spec section 15.1 and section 15.2 . param no. characteristic sym min typ? max units conditions input low voltage i/o ports v il d030 with ttl buffer v ss 0.15v dd v for entire v dd range d030a v ss 0.8v v 4.5v v dd 5.5v d031 with schmitt trigger buffer rc3 and rc4 all others v ss v ss 0.3v dd 0.2v dd v i 2 c compliant for entire v dd range d032 mclr , osc1 (in rc mode) v ss 0.2v dd v d033 osc1 (in xt, hs and lp) v ss 0.3v dd vnote1 input high voltage i/o ports v ih d040 with ttl buffer 2.0 v dd v4.5v v dd 5.5v d040a 0.25v dd + 0.8v v dd v for entire v dd range d041 with schmitt trigger buffer rc3 and rc4 all others 0.7v dd 0.8v dd v dd v dd v v i 2 c compliant for entire v dd range d042 mclr 0.8v dd v dd v d042a osc1 (xt, hs and lp) 0.7v dd v dd vnote1 d043 osc1 (in rc mode) 0.9v dd v dd v d070 portb weak pull-up current i purb 50 250 400 m av dd = 5v, v pin = v ss input leakage current (notes 2, 3) d060 i/o ports (digital) i il 1 m avss v pin v dd , pin at hi- impedance d060a i/o ports (ra0-ra3, ra5, rb2, rb3 analog) i il 100 na vss v pin v dd , pin at hi- impedance d061 mclr , ra4/t0cki 5 m avss v pin v dd d063 osc1 5 m avss v pin v dd , xt, hs and lp osc configuration output low voltage d080 i/o ports v ol 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d083 osc2/clkout (rc osc config) 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c77x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 155 output high voltage d090 i/o ports (note 3) v oh v dd - 0.7 vi oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d092 osc2/clkout (rc osc config) v dd - 0.7 vi oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d150* open-drain high voltage v od 8.5 v ra4 pin capacitive loading specs on output pins d100 osc2 pin c osc2 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 d102 all i/o pins and osc2 (in rc mode) scl, sda in i 2 c mode c io c b 50 400 pf pf dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial and 0c t a +70c for commercial operating voltage v dd range as described in dc spec section 15.1 and section 15.2 . param no. characteristic sym min typ? max units conditions * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c77x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin.
pic16c77x ds30275a-page 156 advance information ? 1999 microchip technology inc. 15.4 dc characteristics: vref table 15-2 electrical characteristics: v ref dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial and 0c t a +70c for commercial operating voltage v dd range as described in dc spec section 15.1 and section 15.2 . param no. characteristic symbol min typ? max units conditions d400 output voltage vrl 2.0 2.048 2.1 v v dd 3 2.5v vrh 4.0 4.096 4.2 v v dd 3 4.5v d401a vrl quiescent supply current d iv rl 70 tbd m a no load on vrl. d401b vrh quiescent supply current d iv rh 70 tbd m a no load on vrh. d402 ouput voltage drift tcv out 15* 50* ppm/c note 1 d404 external load source i vrefso 5* ma d405 external load sink i vrefsi -5* ma d406 load regulation d v out / d i out 1tbd* mv/ma isource = 0 ma to 5ma 1 tbd* isink = 0 ma to 5ma d407 line regulation d v out / d v dd 50* m v/v * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: production tested at t amb = 25c. specifications over temp limits guaranteed by characterization.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 157 figure 15-1: low-voltage detect characteristics table 15-3 electrical characteristics: lvd dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial and 0c t a +70c for commercial operating voltage v dd range as described in dc spec section 15.1 and section 15.2 . param no. characteristic symbol min typ? max units conditions d420 lvd voltage lvv = 0100 2.5 2.58 2.66 v lvv = 0101 2.7 2.78 2.86 v lvv = 0110 2.8 2.89 2.98 v lvv = 0111 3.0 3.1 3.2 v lvv = 1000 3.3 3.41 3.52 v lvv = 1001 3.5 3.61 3.72 v lvv = 1010 3.6 3.72 3.84 v lvv = 1011 3.8 3.92 4.04 v lvv = 1100 4.0 4.13 4.26 v lvv = 1101 4.2 4.33 4.46 v lvv = 1110 4.5 4.64 4.78 v d421 supply current d i lvd 10 20 m a d422* lvd voltage drift temperature coefficient tcv out 15 50 ppm/c d423* lvd voltage drift with respect to v dd regulation d v lvd / d v dd 50 m v/v d424* low-voltage detect hysteresis v lhys tbd 100 mv * these parameters are characterized but not tested. note 1: production tested at tamb = 25c. specifications over temp limits ensured by characterization. v lvd v lhys lvdif v dd (lvdif set by hardware) (lvdif can be cleared in software anytime during the gray area)
pic16c77x ds30275a-page 158 advance information ? 1999 microchip technology inc. figure 15-2: brown-out reset characteristics table 15-4 electrical characteristics: bor dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial and 0c t a +70c for commercial operating voltage v dd range as described in dc spec section 15.1 and section 15.2 . param no. characteristic symbol min typ max units conditions d005 bor voltage borv1:0 = 11 v bor 2.5 2.58 2.66 v borv1:0 = 10 2.7 2.78 2.86 borv1:0 = 01 4.2 4.33 4.46 borv1:0 = 00 4.5 4.64 4.78 d006* bor voltage drift temperature coef- ficient tcv out 15 50 ppm/c d006a* bor voltage drift with respect to v dd regulation d v bor / d v dd 50 m v/v d007 brown-out hysteresis v bhys tbd 100mv d022a supply current d i bor 10 20 m a * these parameters are characterized but not tested. note 1: production tested at t amb = 25c. specifications over temp limits ensured by characterization. v bor v bhys reset (due to bor) v dd (device in brown-out reset) (device not in brown-out reset) 72 ms time out
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 159 15.5 ac characteristics: pic16c77x (commercial, industrial) 15.5.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t ffrequency ttime lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition
pic16c77x ds30275a-page 160 advance information ? 1999 microchip technology inc. figure 15-3: load conditions v dd /2 c l r l pin pin v ss v ss c l r l =464 w c l = 50 pf for all pins except osc2, but including portd and porte outputs as ports 15 pf for osc2 output note: portd and porte are not implemented on the pic16c773. load condition 1 load condition 2
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 161 15.5.2 timing diagrams and specifications figure 15-4: external clock timing osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 table 15-5 external clock timing requirements parameter no. sym characteristic min typ? max units conditions fosc external clkin frequency (note 1) dc 4 mhz xt and rc osc mode dc 4 mhz hs osc mode (-04) dc 20 mhz hs osc mode (-20) dc 200 khz lp osc mode oscillator frequency (note 1) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 5 20 200 mhz khz hs osc mode lp osc mode 1tosc external clkin period (note 1) 250 ns xt and rc osc mode 250 ns hs osc mode (-04) 50 ns hs osc mode (-20) 5 m s lp osc mode oscillator period (note 1) 250 ns rc osc mode 250 10,000 ns xt osc mode 250 250 ns hs osc mode (-04) 50 250 ns hs osc mode (-20) 5 m s lp osc mode 2t cy instruction cycle time (note 1) 200 t cy dc ns t cy = 4/f osc 3* tosl, to s h external clock in (osc1) high or low time 100 ns xt oscillator 2.5 m s lp oscillator 15 ns hs oscillator 4* tosr, to s f external clock in (osc1) rise or fall time 25 ns xt oscillator 50 ns lp oscillator 15 ns hs oscillator * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clkin pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices.
pic16c77x ds30275a-page 162 advance information ? 1999 microchip technology inc. figure 15-5: clkout and i/o timing table 15-6 clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - 0.25t cy + 25 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 50 150 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) pic16 c 77x 100 ns pic16 lc 77x 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0 ns 20* tior port output rise time pic16 c 77x 1025ns pic16 lc 77x 60 ns 21* tiof port output fall time pic16 c 77x 1025ns pic16 lc 77x 60 ns 22??* tinp int pin high or low time t cy ns 23??* trbp rb7:rb4 change int high or low time t cy ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . note: refer to figure 15-3 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 163 figure 15-6: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 15-7: brown-out reset timing table 15-7 reset, watchdog timer, oscillator start-up timer,power-up timer, and brown-out reset requirements parameter no. sym characteristic min typ? max units conditions 30* tmcl mclr pulse width (low) 100 nsv dd = 5v, -40c to +85c 31* twdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40c to +85c 32* tost oscillation start-up timer period 1024t osc t osc = osc1 period 33* tpwrt power up timer period 28 72 132 ms v dd = 5v, -40c to +85c 34* t ioz i/o hi-impedance from mclr low or watchdog timer reset 100 ns 35* t bor brown-out reset pulse width 100 m sv dd v bor (d005) * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 15-3 for load conditions. v dd bv dd 35
pic16c77x ds30275a-page 164 advance information ? 1999 microchip technology inc. figure 15-8: bandgap start-up time table 15-8 bandgap start-up time parameter no. sym characteristic min typ? max units conditions 36* t bgap bandgap start-up time 30tbd m s defined as the time between the instant that the bandgap is enabled and the moment that the bandgap reference voltage is stable. * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v bgap = 1.2v v bgap enable bandgap bandgap stable t bgap
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 165 table 15-9 a/d converter characteristics : param no. sym characteristic min typ? max units conditions a01 n r resolution 12 bits bit min. resolution for a/d is 1 mv, v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a03 e il integral error +/-2 lsb v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a04 e dl differential error +2 lsb -1 lsb no missing codes to 12-bits v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a06 e off offset error less than 2 lsb v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a07 e gn gain error +/- 2lsb lsb v ref + = av dd = 4.096v, v ref - = av ss = 0v, v ref - v ain v ref + a10 monotonicity guaranteed (3) av ss v ain v ref + a20 v ref reference voltage (v ref + v ref -) 4.096 v dd +0.3v v absolute minimum electrical spec to ensure 12-bit accuracy. a21 v ref + reference v high (a vdd or v ref +) v ref - av dd v min. resolution for a/d is 1 mv a22 v ref - reference v low (a vss or v ref -) av ss v ref + v min. resolution for a/d is 1 mv a25 v ain analog input voltage v refl v refh v a30 z ain recommended impedance of analog voltage source 2.5k w a50 i ref v ref input current (note 2) 10 m a during v ain acquisition. based on differential of v hold to v ain . to charge c hold see section 11.0 . during a/d conversion cycle. * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power down current spec includes a ny such leakage from the a/d module. 2: v ref current is from external v ref +, or v ref -, or av ss , or av dd pin, whichever is selected as reference input. 3: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes.
pic16c77x ds30275a-page 166 advance information ? 1999 microchip technology inc. figure 15-9: a/d conversion timing (normal mode) table 15-10 a/d conversion requirements parameter no. sym characteristic min typ? max units conditions 130* t ad a/d clock period 1.6 m s tosc based, v ref 3 2.5v 3.0 m s tosc based, v ref full range 130* t ad a/d internal rc oscillator period 3.0 6.0 9.0 m s adcs1:adcs0 = 11 (rc mode) at v dd = 2.5v 2.0 4.0 6.0 m sat v dd = 5.0v 131* t cnv conversion time (not including acquisition time) (note 1) 13t ad t ad set go bit to new data in a/d result register 132* t acq acquisition time note 2 5* 11.5 m s m s the minimum time is the amplifier settling time. this may be used if the new input voltage has not changed by more than 1lsb (i.e 1mv @ 4.096v) from the last sam- pled voltage (as stated on c hold ). 134* t go q4 to a/d clock start t osc /2 if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 11.6 for minimum conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 987 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1/2 tcy 6 134
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 167 figure 15-10: a/d conversion timing (sleep mode) table 15-11 a/d conversion requirements parameter no. sym characteristic min typ? max units conditions 130* t ad a/d clock period 1.6 m sv ref 3 2.5v tbd m sv ref full range 130* t ad a/d internal rc oscillator period 3.0 6.0 9.0 m s adcs1:adcs0 = 11 (rc mode) at v dd = 3.0v 2.0 4.0 6.0 m sat v dd = 5.0v 131* t cnv conversion time (not including acquisition time)(note 1) 13t ad 132* t acq acquisition time note 2 5* 11.5 m s m s the minimum time is the amplifier settling time. this may be used if the new input voltage has not changed by more than 1lsb (i.e 1mv @ 4.096v) from the last sam- pled voltage (as stated on c hold ). 134* t go q4 to a/d clock start t osc /2 + t cy if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see section 11.6 for minimum conditions. 131 130 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 9 7 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 134 6 8 132
pic16c77x ds30275a-page 168 advance information ? 1999 microchip technology inc. figure 15-11: timer0 and timer1 external clock timings table 15-12 timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns must also meet parameter 42 with prescaler 10 ns 42* tt0p t0cki period no prescaler t cy + 40 ns with prescaler greater of: 20 or t cy + 40 n ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 77x 15 ns pic16 lc 77x 25 ns asynchronous pic16 c 77x 30 ns pic16 lc 77x 50 ns 46* tt1l t1cki low time synchronous, prescaler = 1 0.5t cy + 20 ns must also meet parameter 47 synchronous, prescaler = 2,4,8 pic16 c 77x 15 ns pic16 lc 77x 25 ns asynchronous pic16 c 77x 30 ns pic16 lc 77x 50 ns 47* tt1p t1cki input period synchronous pic16 c 77x greater of : 30 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) pic16 lc 77x greater of : 50 or t cy + 40 n ns n = prescale value (1, 2, 4, 8) asynchronous pic16 c 77x 60 ns pic16 lc 77x 100 ns ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc 50 khz 48 tckeztmr1 delay from external clock edge to timer increment 2tosc 7tosc * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 15-3 for load conditions. 46 47 45 48 41 42 40 ra4/t0cki rc0/t1oso/t1cki tmr0 or tmr1
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 169 figure 15-12: capture/compare/pwm timings (ccp1 and ccp2) table 15-13 capture/compare/pwm requirements (ccp1 and ccp2) parameter no. sym characteristic min typ? max units conditions 50* tccl ccp1 and ccp2 input low time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 77x 10 ns pic16 lc 77x 20 ns 51* tcch ccp1 and ccp2 input high time no prescaler 0.5t cy + 20 ns with prescaler pic16 c 77x 10 ns pic16 lc 77x 20 ns 52* tccp ccp1 and ccp2 input period 3t cy + 40 n ns n = prescale value (1,4 or 16) 53* tccr ccp1 and ccp2 output fall time pic16 c 77x 1025ns pic16 lc 77x 2545ns 54* tccf ccp1 and ccp2 output fall time pic16 c 77x 1025ns pic16 lc 77x 2545ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 15-3 for load conditions. and rc2/ccp1 (capture mode) 50 51 52 53 54 rc1/t1osi/ccp2 and rc2/ccp1 (compare or pwm mode) rc1/t1osi/ccp2
pic16c77x ds30275a-page 170 advance information ? 1999 microchip technology inc. figure 15-13: parallel slave port timing (pic16c774) table 15-14 parallel slave port requirements (pic16c774) parameter no. sym characteristic min typ? max units conditions 62* tdtv2wrh data in valid before wr - or cs - (setup time) 20 25 ns ns extended temperature range only 63* twrh2dti wr - or cs - to dataCin invalid (hold time) pic16 c 774 20 ns pic16 lc 774 35 ns 64* trdl2dtv rd and cs to dataCout valid 80 90 ns ns extended temperature range only 65* trdh2dti rd - or cs to dataCout invalid 10 30 ns * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 15-3 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 171 figure 15-14: usart synchronous transmission (master/slave) timing table 15-15 usart synchronous transmission requirements figure 15-15: usart synchronous receive (master/slave) timing table 15-16 usart synchronous receive requirements param no. sym characteristic min typ? max units conditions 120* tckh2dtv sync xmit (master & slave) clock high to data out valid pic16 c 774/773 80 ns pic16 lc 774/773 100 ns 121* tckrf clock out rise time and fall time (master mode) pic16 c 774/773 45 ns pic16 lc 774/773 50 ns 122* tdtrf data out rise time and fall time pic16 c 774/773 45 ns pic16 lc 774/773 50 ns * these parameters are characterized but not tested. ?: data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. parameter no. sym characteristic min typ? max units conditions 125* tdtv2ckl sync rcv (master & slave) data setup before ck (dt setup time) 15 ns 126* tckl2dtl data hold after ck (dt hold time) 15 ns * these parameters are characterized but not tested. ?: data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 15-3 for load conditions. 121 121 122 rc6/tx/ck rc7/rx/dt pin pin 120 note: refer to figure 15-3 for load conditions. 125 126 rc6/tx/ck rc7/rx/dt pin pin
pic16c77x ds30275a-page 172 advance information ? 1999 microchip technology inc. notes:
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 173 16.0 dc and ac characteristics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested . in some graphs or tables, the data presented are outside specified operating range (i.e., outside specified v dd range). this is for information only and devices are guaranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'typical' represents the mean of the distribution at 25 c. 'max' or 'min' represents (mean + 3 s ) or (mean - 3 s ) respectively, where s is standard deviation, over the whole temperature range. graphs and tables not available at this time.
pic16c77x ds30275a-page 174 advance information ? 1999 microchip technology inc. notes:
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 175 17.0 packaging information 17.1 package marking information 28-lead soic xxxxxxxxxxxxxxxxxxxxxxxx aabbcde example pic16c773-20/so xxxxxxxxxxxxxxxxxxxx aabbcde 28-lead pdip (skinny dip) example pic16c773-20/sp 9917hat 9910saa aabbcae xxxxxxxxxxxx xxxxxxxxxxxx 28-lead ssop 9817sbp 20i/ss pic16c773 example legend: mm...m microchip part number information xx...x customer specific information* aa year code (last 2 digits of calendar year) bb week code (week of january 1 is week 01) c facility code of the plant at which wafer is manufactured o = outside vendor c = 5 line s = 6 line h = 8 line d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx aabbcde 28-lead cerdip windowed xxxxxxxxxxx pic16c774/jw example 9905hat xxxxxxxxxxx
pic16c77x ds30275a-page 176 advance information ? 1999 microchip technology inc. package marking information (contd) xxxxxxxxxxxxxxxxxx aabbcde 40-lead pdip example pic16c774-04/p xxxxxxxxxxxxx aabbcde 40-lead cerdip windowed xxxxxxxxxxxxx pic16c774/jw example 9912saa 9905hat 44-lead tqfp xxxxxxxxxxxx aabbcde xxxxxxxxxxxx xxxxxxxxxxxx example -04/pt pic16c774 44-lead plcc xxxxxxxxxxxx aabbcde xxxxxxxxxxxx xxxxxxxxxxxx 44-lead mqfp example pic16c774 -04/l example -20/pq pic16c774 9904sat 9911hat 9903sat xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxx xxxxxxxxxxxx aabbcde xxxxxxxxxxxx xxxxxxxxxxxx
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 177 17.2 k04-070 28-lead skinny plastic dual in-line (sp) C 300 mil * controlling parameter. ? dimension b1 does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension b1. ? dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions d or e. 0.320 0.270 0.280 1.345 0.125 0.015 0.070 0.140 0.008 0.000 0.040 0.016 mold draft angle bottom mold draft angle top overall row spacing radius to radius width molded package width tip to seating plane base to seating plane top of lead to seating plane top to seating plane upper lead width lower lead width pcb row spacing package length lead thickness shoulder radius number of pins dimension limits pitch units e ? b eb e1 a a1 a2 l d ? a c r n b1 ? b p min min 0.295 0.288 5 5 10 0.350 0.283 10 0.380 0.295 15 15 0.090 1.365 0.130 0.020 0.150 0.010 0.005 nom inches* 28 0.053 0.019 0.100 0.300 1.385 0.135 0.025 0.110 0.160 0.012 0.010 0.065 0.022 max 7.49 7.30 7.11 8.89 7.18 5 8.13 6.86 5 10 10 15 15 9.65 7.49 34.67 3.30 0.51 2.29 3.81 0.25 0.13 1.33 0.48 2.54 7.62 millimeters 1.78 34.16 3.18 0.38 3.56 0.20 0.00 1.02 0.41 nom 2.79 35.18 3.43 0.64 4.06 0.30 0.25 max 28 1.65 0.56 n 1 2 r d e c eb b e1 a p l a1 b b1 a a2
pic16c77x ds30275a-page 178 advance information ? 1999 microchip technology inc. 17.3 k04-080 28-lead ceramic dual in-line with window (jw) C 300 mil * controlling parameter. n 1 2 r overall row spacing radius to radius width package length tip to seating plane base to seating plane top of lead to seating plane top to seating plane shoulder radius upper lead width lower lead width pcb row spacing dimension limits window width window length package width lead thickness pitch number of pins units 0.170 a 0.130 w1 w2 0.290 d e1 eb e a2 l a1 1.430 0.345 0.255 0.285 0.135 0.015 0.107 b r c b1 n p 0.016 0.008 0.010 0.050 0.098 min millimeters 4.32 0.195 0.183 0.310 0.150 0.425 0.285 0.295 1.485 0.145 0.030 0.143 0.140 0.300 0.385 0.270 0.290 1.458 0.140 0.023 0.125 0.13 0.29 36.32 8.76 6.48 7.24 3.43 0.00 2.72 0.012 0.015 0.065 0.021 0.102 max nom 0.010 0.013 0.058 0.019 0.100 0.300 28 inches* 0.41 0.20 0.25 1.27 2.49 min 4.95 4.64 0.31 0.15 10.80 7.24 7.49 37.72 3.68 0.76 3.63 0.14 0.3 37.02 6.86 9.78 7.37 0.57 3.56 3.18 0.30 0.38 1.65 0.53 2.59 nom 28 0.47 0.32 0.25 1.46 2.54 7.62 max d w2 w1 e c e1 eb p a1 l b1 b a2 a
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 179 17.4 k04-052 28-lead plastic small outline (so) C wide, 300 mil min p pitch mold draft angle bottom mold draft angle top lower lead width radius centerline gull wing radius shoulder radius chamfer distance outside dimension molded package width molded package length shoulder height overall pack. height lead thickness foot angle foot length standoff number of pins b a b ? c f x a2 a1 a n e1 l l1 r1 r2 e ? d ? dimension limits units 1.27 0.050 8 12 12 0.017 0 0.014 0 0.019 15 15 0.011 0.015 0.016 0.005 0.005 0.020 0.407 0.296 0.706 0.008 0.058 0.099 28 0.394 0.011 0.009 0.010 0 0.005 0.005 0.010 0.292 0.700 0.004 0.048 0.093 0.419 0.012 0.020 0.021 0.010 0.010 0.029 48 0.299 0.712 0.011 0.068 0.104 0.36 0 0 12 12 0.42 15 15 0.48 10.33 17.93 10.01 0.23 0.25 0.28 0.13 0.13 0.25 0 7.42 0.10 1.22 2.36 17.78 10.64 0.41 4 0.27 0.38 0.13 0.13 0.50 0.53 0.30 0.51 0.25 0.25 0.74 7.51 0.19 28 2.50 1.47 18.08 7.59 0.28 2.64 1.73 nom inches* max nom millimeters min max n 1 2 r1 r2 d p b e1 e l1 l c b 45 x f a1 a a a2 * controlling parameter. ? dimension b does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension b. ? dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions d or e.
pic16c77x ds30275a-page 180 advance information ? 1999 microchip technology inc. 17.5 k04-073 28-lead plastic shrink small outline (ss) C 5.30 mm dimension limits mold draft angle bottom mold draft angle top lower lead width lead thickness radius centerline gull wing radius shoulder radius outside dimension molded package width molded package length shoulder height overall pack. height number of pins foot angle foot length standoff pitch b a b ? e ? l c l1 f r1 r2 e1 a2 d ? a1 a n p units max nom min max nom min 10 10 0.38 0.22 0.25 0.64 0.25 0.25 7.90 5.38 10.33 0.21 1.17 1.99 0.012 0 0.010 0 5 5 10 0.015 10 0.007 0.005 0.020 0.005 0.005 0.306 0.208 0.402 0.005 0.036 0.073 0.026 0.205 0.015 0.005 0.000 0 0.005 0.005 0.301 0.396 0.002 0.026 0.068 0.212 4 0.025 0.009 0.010 8 0.010 0.010 0.311 28 0.407 0.008 0.046 0.078 0.25 0 0 5 0.32 5 5.20 0.13 0.00 0.38 0.13 0.13 7.65 0 10.07 0.05 0.66 1.73 5.29 0.51 0.18 0.13 4 0.13 0.13 7.78 10.20 0.13 0.91 1.86 0.65 28 8 inches millimeters* n 1 2 r1 r2 d p b e e1 l l1 b c f a a1 a2 a * controlling parameter. ? dimension b does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension b. ? dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions d or e.
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 181 17.6 k04-016 40-lead plastic dual in-line (p) C 600 mil * controlling parameter. ? dimension b1 does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension b1. ? dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions d or e. n 2 1 r top to seating plane mold draft angle bottom mold draft angle top overall row spacing radius to radius width molded package width tip to seating plane base to seating plane top of lead to seating plane package length e1 b eb a l e ? d ? a2 a1 0.670 0.585 0.540 2.023 0.135 0.040 0.113 0.545 5 5 0.630 0.125 0.530 2.013 0.020 0.073 0.565 10 0.610 10 0.130 0.535 2.018 0.020 0.093 16.00 13.84 13.46 51.13 3.18 0.51 1.85 15 15 14.35 5 5 10 15.49 10 3.30 13.59 51.26 0.51 2.36 14.86 17.02 15 15 13.72 51.38 3.43 1.02 2.87 pcb row spacing lead thickness shoulder radius upper lead width lower lead width pitch number of pins dimension limits units p c a r b b1 ? n 0.160 0.011 0.010 0.055 0.020 nom inches* 0.110 0.009 0.000 0.045 0.016 min 0.100 0.160 0.010 0.005 0.050 0.018 40 0.600 max 2.79 0.23 0.00 1.14 0.41 min 2.54 4.06 0.25 0.13 1.27 0.46 nom millimeters 15.24 40 4.06 0.28 0.25 1.40 0.51 max a1 d e c b eb e1 a p l b b1 a a2
pic16c77x ds30275a-page 182 advance information ? 1999 microchip technology inc. 17.7 k04-014 40-lead ceramic dual in-line with window (jw) C 600 mil * controlling parameter. n 1 2 r window diameter overall row spacing radius to radius width package width package length tip to seating plane base to seating plane top of lead to seating plane top to seating plane lead thickness shoulder radius upper lead width lower lead width number of pins pcb row spacing dimension limits pitch e1 w eb d e l a2 a1 a c p b1 r b n 9.14 18.03 15.24 13.36 52.32 3.68 3.89 5.59 0.36 0.25 0.58 2.59 max 0.014 0.011 0.008 0.350 0.660 0.580 0.520 2.050 0.140 0.045 0.135 0.205 0.560 0.340 0.610 0.514 2.040 0.135 0.030 0.117 0.190 0.600 0.360 0.710 0.526 2.060 0.145 0.060 0.153 0.220 0.005 0.053 0.020 0.100 0.600 nom 0.000 0.050 0.016 0.098 min 40 0.102 0.010 0.055 0.023 max 0.28 0.20 14.22 15.49 8.64 13.06 51.82 3.43 0.00 2.97 4.83 14.73 16.76 8.89 13.21 52.07 3.56 1.14 3.43 5.21 min 2.49 1.27 0.00 0.41 2.54 1.33 0.13 0.50 15.24 nom 40 1.52 1.40 d w e c eb e1 p l a1 b1 b a a2 units inches* millimeters
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 183 17.8 k04-076 44-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.1 mm lead form 0.025 0.390 0.390 0.463 0.463 0.012 0.004 0.003 0.005 0.003 0.003 0.002 0.015 0.039 p mold draft angle bottom mold draft angle top pin 1 corner chamfer molded pack. width molded pack. length outside tip width outside tip length lower lead width lead thickness radius centerline gull wing radius shoulder radius shoulder height overall pack. height pins along width number of pins foot length foot angle standoff d ? b x a e ? l d1 e1 b ? c l1 f a1 r1 r2 a2 n1 a n dimension limits pitch units min 0.398 0.394 5 5 12 0.035 0.394 10 0.045 0.398 15 15 0.010 0 0.472 0.472 0.015 0.006 0.008 3.5 0.025 0.006 0.003 0.004 0.043 11 44 0.015 0.482 0.482 0.018 0.008 0.013 7 0.008 0.010 0.006 0.035 0.047 10.10 10.00 9.90 12 10 0.89 10.00 5 0.64 9.90 5 15 15 1.14 10.10 12.00 12.00 0.38 0.15 0.20 3.5 0.25 0.14 0.08 0.10 0.64 1.10 11 44 0.13 11.75 11.75 0.30 0.09 0.08 0 0.38 0.08 0.08 0.05 1.00 0.38 12.25 12.25 0.45 0.20 0.33 7 0.89 0.20 0.25 0.15 1.20 min nom inches 0.031 max 0.80 millimeters* nom max x x 45 n 1 2 r2 r1 l1 l b c f d1 d b p # leads = n1 e e1 a a1 a2 a * controlling parameter. ? dimension b does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension b. ? dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions d or e. jedec equivalent:ms-026 acb
pic16c77x ds30275a-page 184 advance information ? 1999 microchip technology inc. 17.9 k04-071 44-lead plastic quad flatpack (pq) 10x10x2 mm body, 1.6/0.15 mm lead form * controlling parameter. ? dimension b does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension b. ? dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions d or e. jedec equivalent:ms-022 ab 0.025 0.390 0.390 0.510 0.510 0.012 0.005 0.011 0.015 0.005 0.005 0.002 0.032 0.079 p pitch mold draft angle bottom mold draft angle top pin 1 corner chamfer molded pack. width molded pack. length outside tip width outside tip length lower lead width radius centerline gull wing radius shoulder radius shoulder height overall pack. height pins along width lead thickness foot angle foot length standoff number of pins b a x e ? d ? c f a2 a1 a n1 n r2 e1 d1 b ? l1 l r1 dimension limits units min 0.80 0.031 0.635 12.95 12.95 0.035 0.394 0.394 5 5 10 12 15 15 0.045 0.398 0.398 0.012 0.520 0.520 0.015 0.007 0.016 0.020 03.5 0.005 0.006 0.044 0.086 11 44 0.015 0.009 0.530 0.530 0.018 0.021 0.025 7 0.010 0.010 0.056 0.093 5 5 9.90 9.90 10 12 10.00 10.00 0.89 1.143 10.10 10.10 15 15 0.30 0.13 0.13 0.30 0 0.28 0.38 0.18 13.20 13.20 0.37 3.5 0.41 0.51 0.13 0.05 0.81 2.00 0.13 0.15 1.11 11 2.18 44 0.38 13.45 13.45 0.45 0.23 0.53 0.64 7 0.25 0.25 1.41 2.35 min nom inches max millimeters* nom max x x 45 n 1 2 r2 r1 d d1 b p e1 e # leads = n1 l1 l c b f a a1 a a2
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 185 17.10 k04-048 44-lead plastic leaded chip carrier (l) C square * controlling parameter. ? dimension b1 does not include dam-bar protrusions. dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension b1. ? dimensions d and e do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions d or e. jedec equivalent:mo-047 ac 0.015 0.003 0.050 0.015 0.026 0.008 0.610 0.610 0.650 0.650 0.685 0.685 0.000 0.040 0.024 0.015 0.095 0.165 min p pitch mold draft angle bottom mold draft angle top j-bend inside radius shoulder inside radius upper lead length lower lead width upper lead width lead thickness pins along width footprint length footprint width molded pack. length molded pack. width overall pack. length overall pack. width corner chamfer (other) corner chamfer (1) side 1 chamfer dim. shoulder height overall pack. height standoff r2 r1 a b l b b1 ? d2 e2 ch2 ch1 a3 a2 e1 c n1 e ? d ? d1 a1 a number of pins dimension limits units n 1.27 0.050 0 0 0.005 0.025 5 5 0.058 0.018 0.029 0.035 0.010 0.065 0.021 0.032 10 10 0.690 0.620 0.010 0.620 11 0.653 0.653 0.690 0.005 0.045 0.029 0.023 0.103 0.173 0.695 0.012 0.630 0.630 0.656 0.656 0.695 0.010 0.050 0.034 0.030 0.110 0.180 0.64 0.13 1.46 0.46 0.74 0.08 0.38 0 0 1.27 0.38 0.66 5 5 0.25 0.89 10 10 1.65 0.53 0.81 0.25 15.75 15.75 16.59 16.59 17.53 17.53 0.13 1.14 0.74 0.57 2.60 4.38 17.40 15.49 0.20 15.49 16.51 16.51 17.40 0.00 1.02 0.61 0.38 2.41 4.19 17.65 11 16.00 0.30 16.00 16.66 16.66 17.65 0.25 1.27 0.86 0.76 2.79 4.57 inches* nom 44 max millimeters min nom max 44 1 ch2 x 45 n ch1 x 45 2 b r2 a1 r1 c e2 d1 d # leads = n1 e1 e a p l a3 a2 a 35 b1 b d2
pic16c77x ds30275a-page 186 advance information ? 1999 microchip technology inc. notes:
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 187 appendix a: revision history appendix b: device differences the differences between the devices in this data sheet are listed in ta b l e b - 1 . appendix c: conversion considerations considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in the following: pic16c774 vs. pic16c74a ? ra2 added v ref - and vrl ? ra3 added v ref + and vrh ? ra5 removed ss ?pin 11 av dd vs. v dd ?pin 12 av ss vs. v ss ? rb1 added ss , ss is now st vs. ttl ? rb2 added an8 ? rb3 added an9 and lvdin pic16c773 vs. pic16c73a ? ra2 added v ref - and vrl ? ra3 added v ref + and vrh ?pin 7 av dd vs. removed ra5/ss /an4 ?pin 8 av ss vs. v ss ? rb1 added ss , ss is now st vs. ttl ? rb2 added an8 ? rb3 added an9 and lvdin program memory differences none data memory differences 1. data memory size has increased to 256 from 192 by adding bank 2. 2. bank 1 locations 0xf0 - 0xff are now common ram locations across banks 0-3. peripheral differences 1. 12-bit a/d replaces 8-bit a/d. 2. master synchronous serial port replace synchronous serial port. 3. usart adds 9-bit address mode to module. 4. bandgap voltage reference added. 5. low-voltage detect module added. 6. selectable brown-out reset voltages added. version date revision description a 99 this is a new data sheet. however, the devices described in this data sheet are the upgrades to the devices found in the pic16c7x data sheet , ds30390e. table b-1: device differences difference pic16c773 pic16c774 a/d 6 channels, 12 bits 10 channels, 12 bits parallel slave port no yes packages 28-pin pdip, 28-pin windowed cerdip, 28-pin soic, 28-pin ssop 40-pin pdip, 40-pin windowed cerdip, 44-pin tqfp, 44-pin mqfp, 44-pin plcc
pic16c77x ds30275a-page 188 advance information ? 1999 microchip technology inc. notes:
pic16c77x ? 1999 microchip technology inc. preliminary ds30275a-page 189 index a a/d ................................................................................... 117 a/d converter enable (adie bit) ............................... 19 a/d converter flag (adif bit) ................................... 20 adcon0 register .................................................... 117 adcon1 register ............................................ 117, 118 adres register ...................................................... 117 analog port pins ...................................... 7, 8, 9, 36, 37 block diagram .......................................................... 120 configuring analog port ........................................... 119 conversion time ....................................................... 125 conversions ............................................................. 121 converter characteristics .................. 156, 157, 158, 165 faster conversion - lower resolution tradeoff ...... 125 internal sampling switch (rss) impedence ............. 123 operation during sleep ........................................... 126 sampling requirements ........................................... 123 sampling time ......................................................... 123 source impedance ................................................... 123 special event trigger (ccp) ...................................... 49 a/d conversion clock ...................................................... 121 ack .................................................................................... 64 acknowledge data bit, akd ............................................... 56 acknowledge pulse ............................................................ 64 acknowledge sequence enable bit, ake .......................... 56 acknowledge status bit, aks ............................................ 56 adcon0 register ............................................................ 117 adcon1 register .................................................... 117, 118 adres ............................................................................. 117 adres register .......................................... 13, 14, 117, 126 akd .................................................................................... 56 ake .................................................................................... 56 aks .............................................................................. 56, 79 application note an578, "use of the ssp module in the i2c multi-master environment." ................... 63 architecture pic16c63a/pic16c73b block diagram ...................... 5 pic16c65b/pic16c74b block diagram ...................... 6 assembler mpasm assembler .................................................. 147 b banking, data memory ................................................ 11, 16 baud rate generator ......................................................... 73 bf .................................................................... 54, 64, 79, 82 block diagrams baud rate generator ................................................. 73 i 2 c master mode ........................................................ 71 i 2 c module ................................................................. 63 ssp (i 2 c mode) ......................................................... 63 ssp (spi mode) ......................................................... 57 bor. see brown-out reset brg ................................................................................... 73 brown-out reset (bor) ................... 127, 131, 132, 133, 134 bor status (bor bit) ................................................ 23 buffer full bit, bf ............................................................... 64 buffer full status bit, bf .................................................... 54 bus arbitration ................................................................... 90 bus collision section ....................................................................... 90 bus collision during a restart condition ...................... 93 bus collision during a start condition ............................... 91 bus collision during a stop condition ............................... 94 c capture (ccp module) ...................................................... 48 block diagram ........................................................... 48 ccp pin configuration .............................................. 48 ccpr1h:ccpr1l registers .................................... 48 changing between capture prescalers .................... 48 software interrupt ...................................................... 48 timer1 mode selection .............................................. 48 capture/compare/pwm (ccp) ......................................... 47 ccp1 ......................................................................... 47 ccp1con register ........................................... 47 ccpr1h register ............................................. 47 ccpr1l register .............................................. 47 enable (ccp1ie bit) .......................................... 19 flag (ccp1if bit) .............................................. 20 rc2/ccp1 pin ................................................. 7, 9 ccp2 ......................................................................... 47 ccp2con register ........................................... 47 ccpr2h register ............................................. 47 ccpr2l register .............................................. 47 enable (ccp2ie bit) .......................................... 21 flag (ccp2if bit) .............................................. 22 rc1/t1osi/ccp2 pin ..................................... 7, 9 interaction of two ccp modules ............................... 47 timer resources ....................................................... 47 ccp1con ......................................................................... 15 ccp1con register ........................................................... 47 ccp1m3:ccp1m0 bits ............................................. 47 ccp1x:ccp1y bits ................................................... 47 ccp2con ......................................................................... 15 ccp2con register ........................................................... 47 ccp2m3:ccp2m0 bits ............................................. 47 ccp2x:ccp2y bits ................................................... 47 ccpr1h register ........................................................ 13, 15 ccpr1l register .............................................................. 15 ccpr2h register ........................................................ 13, 15 ccpr2l register ........................................................ 13, 15 cke ................................................................................... 54 ckp ................................................................................... 55 clock polarity select bit, ckp ............................................ 55 code examples loading the sspbuf register ................................... 58 code protection ....................................................... 127, 141 compare (ccp module) .................................................... 49 block diagram ........................................................... 49 ccp pin configuration .............................................. 49 ccpr1h:ccpr1l registers .................................... 49 software interrupt ...................................................... 49 special event trigger .......................................... 43, 49 timer1 mode selection .............................................. 49 configuration bits ............................................................ 127 conversion considerations .............................................. 187 d d/a ..................................................................................... 54 data memory ..................................................................... 11 bank select (rp1:rp0 bits) ................................ 11, 16 general purpose registers ....................................... 11 register file map ...................................................... 12 special function registers ........................................ 13 data/address bit, d/a ........................................................ 54 dc characteristics pic16c73 ................................................................ 152 pic16c74 ................................................................ 152 development support ...................................................... 145 development tools .......................................................... 145 device differences ........................................................... 187 direct addressing .............................................................. 25
pic16c77x ds30275a-page 190 preliminary ? 1999 microchip technology inc. e errata ................................................................................... 4 external power-on reset circuit ...................................... 132 f firmware instructions ....................................................... 143 flowcharts acknowledge .............................................................. 86 master receiver ......................................................... 83 master transmit ......................................................... 80 restart condition ....................................................... 77 start condition ........................................................... 75 stop condition ........................................................... 88 fsr register .......................................................... 13, 14, 15 fuzzy logic dev. system ( fuzzy tech -mp) .................. 147 g gce ................................................................................... 56 general call address sequence ........................................ 69 general call address support ........................................... 69 general call enable bit, gce ............................................ 56 i i/o ports ............................................................................. 27 i 2 c ...................................................................................... 63 i 2 c master mode receiver flowchart ................................ 83 i 2 c master mode reception ............................................... 82 i 2 c master mode restart condition ................................... 76 i 2 c mode selection ............................................................ 63 i 2 c module acknowledge flowchart ............................................. 86 acknowledge sequence timing .................................. 85 addressing ................................................................. 64 baud rate generator ................................................. 73 block diagram ............................................................ 71 brg block diagram ................................................... 73 brg reset due to sda collision ............................... 92 brg timing ............................................................... 73 bus arbitration ........................................................... 90 bus collision .............................................................. 90 acknowledge ...................................................... 90 restart condition ............................................... 93 restart condition timing (case1) ...................... 93 restart condition timing (case2) ...................... 93 start condition ................................................... 91 start condition timing ................................. 91, 92 stop condition ................................................... 94 stop condition timing (case1) .......................... 94 stop condition timing (case2) .......................... 94 transmit timing ................................................. 90 bus collision timing .................................................... 90 clock arbitration ......................................................... 89 clock arbitration timing (master transmit) ................ 89 conditions to not give ack pulse .............................. 64 general call address support ................................... 69 master mode .............................................................. 71 master mode 7-bit reception timing .......................... 84 master mode operation ............................................. 72 master mode start condition ..................................... 74 master mode transmission ........................................ 79 master mode transmit sequence .............................. 72 master transmit flowchart ........................................ 80 multi-master communication ..................................... 90 multi-master mode ..................................................... 72 operation ................................................................... 63 repeat start condition timing .................................... 76 restart condition flowchart ...................................... 77 slave mode ................................................................ 64 slave reception ........................................................ 65 slave transmission ................................................... 65 sspbuf .................................................................... 64 start condition flowchart .......................................... 75 stop condition flowchart ........................................... 88 stop condition receive or transmit timing ............... 87 stop condition timing ................................................. 87 waveforms for 7-bit reception .................................. 65 waveforms for 7-bit transmission ............................. 66 i 2 c module address register, sspadd ........................... 64 i 2 c slave mode .................................................................. 64 icepic low-cost pic16cxxx in-circuit emulator ......... 145 id locations ............................................................. 127, 141 in-circuit serial programming (icsp) ...................... 127, 141 indf .................................................................................. 15 indf register .............................................................. 13, 14 indirect addressing ............................................................ 25 fsr register ............................................................. 11 instruction format ............................................................ 143 instruction set .................................................................. 143 summary table ....................................................... 144 intcon ............................................................................. 15 intcon register ............................................................... 18 gie bit ....................................................................... 18 inte bit ..................................................................... 18 intf bit ..................................................................... 18 peie bit ..................................................................... 18 rbie bit ..................................................................... 18 rbif bit ............................................................... 18, 30 t0ie bit ...................................................................... 18 t0if bit ...................................................................... 18 inter-integrated circuit (i 2 c) .............................................. 53 internal sampling switch (rss) impedence ...................... 123 interrupt sources ..................................................... 127, 137 block diagram ......................................................... 137 capture complete (ccp) ........................................... 48 compare complete (ccp) ......................................... 49 interrupt on change (rb7:rb4 ) ............................... 30 rb0/int pin, external ...................................... 7, 8, 138 tmr0 overflow .................................................. 40, 138 tmr1 overflow .................................................... 41, 43 tmr2 to pr2 match .................................................. 46 tmr2 to pr2 match (pwm) ................................ 45, 50 usart receive/transmit complete ......................... 97 interrupts, context saving during .................................... 138 interrupts, enable bits a/d converter enable (adie bit) ............................... 19 ccp1 enable (ccp1ie bit) ................................. 19, 48 ccp2 enable (ccp2ie bit) ....................................... 21 global interrupt enable (gie bit) ....................... 18, 137 interrupt on change (rb7:rb4) enable (rbie bit) ........................................................... 18, 138 peripheral interrupt enable (peie bit) ....................... 18 psp read/write enable (pspie bit) ......................... 19 rb0/int enable (inte bit) ........................................ 18 ssp enable (sspie bit) ............................................ 19 tmr0 overflow enable (t0ie bit) ............................. 18 tmr1 overflow enable (tmr1ie bit) ........................ 19 tmr2 to pr2 match enable (tmr2ie bit) ................ 19 usart receive enable (rcie bit) ........................... 19 usart transmit enable (txie bit) ........................... 19
pic16c77x ? 1999 microchip technology inc. preliminary ds30275a-page 191 interrupts, flag bits a/d converter flag (adif bit) ................................... 20 ccp1 flag (ccp1if bit) ................................ 20, 48, 49 ccp2 flag (ccp2if bit) ............................................ 22 interrupt on change (rb7:rb4) flag (rbif bit) ..................................................... 18, 30, 138 psp read/write flag (pspif bit) .............................. 20 rb0/int flag (intf bit) ............................................. 18 ssp flag (sspif bit) ................................................. 20 tmr0 overflow flag (t0if bit) .......................... 18, 138 tmr1 overflow flag (tmr1if bit) ............................ 20 tmr2 to pr2 match flag (tmr2if bit) ..................... 20 usart receive flag (rcif bit) ................................ 20 usart transmit flag (txie bit) ............................... 20 k keeloq evaluation and programming tools ................. 148 m master clear (mclr ) ....................................................... 7, 8 mclr reset, normal operation .............. 131, 133, 134 mclr reset, sleep ............................... 131, 133, 134 memory organization data memory ............................................................. 11 program memory ....................................................... 11 mplab integrated development environment software . 147 multi-master communication ............................................. 90 multi-master mode ............................................................. 72 o opcode field descriptions ............................................ 143 option_reg register ..................................................... 17 intedg bit ................................................................ 17 ps2:ps0 bits ....................................................... 17, 39 psa bit ................................................................. 17, 39 rbpu bit .................................................................... 17 t0cs bit ............................................................... 17, 39 t0se bit ............................................................... 17, 39 osc1/clkin pin ............................................................. 7, 8 osc2/clkout pin ......................................................... 7, 8 oscillator configuration .................................................... 128 hs .................................................................... 128, 133 lp ..................................................................... 128, 133 rc ............................................................ 128, 130, 133 xt .................................................................... 128, 133 oscillator, timer1 ......................................................... 41, 43 oscillator, wdt ................................................................ 139 p p ......................................................................................... 54 packaging ........................................................................ 175 paging, program memory ............................................ 11, 24 parallel slave port (psp) ......................................... 9, 34, 37 block diagram ............................................................ 37 re0/rd /an5 pin .............................................. 9, 36, 37 re1/wr /an6 pin ............................................. 9, 36, 37 re2/cs /an7 pin .............................................. 9, 36, 37 read waveforms ....................................................... 38 read/write enable (pspie bit) .................................. 19 read/write flag (pspif bit) ...................................... 20 select (pspmode bit) .................................. 34, 35, 37 write waveforms ....................................................... 37 pcl register ................................................................ 13, 14 pclath register .................................................. 13, 14, 15 pcon register .......................................................... 23, 133 bor bit ...................................................................... 23 por bit ...................................................................... 23 picdem-1 low-cost picmicro demo board .................. 146 picdem-2 low-cost pic16cxx demo board ................ 146 picdem-3 low-cost pic16cxxx demo board ............. 146 picstart plus entry level development system ...... 145 pie1 register .................................................................... 19 adie bit ..................................................................... 19 ccp1ie bit ................................................................ 19 pspie bit ................................................................... 19 rcie bit ..................................................................... 19 sspie bit ................................................................... 19 tmr1ie bit ................................................................ 19 tmr2ie bit ................................................................ 19 txie bit ..................................................................... 19 pie2 register .................................................................... 21 ccp2ie bit ................................................................ 21 pinout descriptions pic16c63a/pic16c73b .............................................. 7 pic16c65b/pic16c74b .............................................. 8 pir1 register .................................................................... 20 adif bit ..................................................................... 20 ccp1if bit ................................................................. 20 pspif bit ................................................................... 20 rcif bit ..................................................................... 20 sspif bit ................................................................... 20 tmr1if bit ................................................................ 20 tmr2if bit ................................................................ 20 txif bit ...................................................................... 20 pir2 register .................................................................... 22 ccp2if bit ................................................................. 22 pointer, fsr ...................................................................... 25 por. see power-on reset porta ...................................................................... 7, 8, 15 analog port pins ...................................................... 7, 8 initialization ................................................................ 27 porta register ........................................................ 27 ra3:ra0 and ra5 port pins ..................................... 28 ra4/t0cki pin .................................................. 7, 8, 28 ra5/ss /an4 pin .......................................................... 8 trisa register .......................................................... 27 porta register ........................................................ 13, 126 portb ...................................................................... 7, 8, 15 initialization ................................................................ 29 portb register ........................................................ 29 pull-up enable (rbpu bit) ......................................... 17 rb0/int edge select (intedg bit) .......................... 17 rb0/int pin, external ..................................... 7, 8, 138 rb3:rb0 port pins .................................................... 29 rb7:rb4 interrupt on change ................................. 138 rb7:rb4 interrupt on change enable (rbie bit) .... 18, 138 rb7:rb4 interrupt on change flag (rbif bit) ... 18, 30, 138 rb7:rb4 port pins .................................................... 30 trisb register .......................................................... 29 portb register ........................................................ 13, 126 portc ...................................................................... 7, 9, 15 block diagram ........................................................... 32 initialization ................................................................ 32 portc register ........................................................ 32 rc0/t1oso/t1cki pin ........................................... 7, 9 rc1/t1osi/ccp2 pin ............................................. 7, 9 rc2/ccp1 pin ......................................................... 7, 9 rc3/sck/scl pin ................................................... 7, 9
pic16c77x ds30275a-page 192 preliminary ? 1999 microchip technology inc. rc4/sdi/sda pin .................................................... 7, 9 rc5/sdo pin ........................................................... 7, 9 rc6/tx/ck pin .................................................. 7, 9, 98 rc7/rx/dt pin ............................................ 7, 9, 98, 99 trisc register .................................................... 32, 97 portc register ................................................................ 13 portd ..................................................................... 9, 15, 37 block diagram ............................................................ 34 parallel slave port (psp) function ............................ 34 portd register ........................................................ 34 trisd register .......................................................... 34 portd register ................................................................ 13 porte ........................................................................... 9, 15 analog port pins .............................................. 9, 36, 37 block diagram ............................................................ 35 input buffer full status (ibf bit) ................................ 35 input buffer overflow (ibov bit) ................................ 35 output buffer full status (obf bit) ............................ 35 porte register ........................................................ 35 psp mode select (pspmode bit) ................ 34, 35, 37 re0/rd /an5 pin .............................................. 9, 36, 37 re1/wr /an6 pin ............................................. 9, 36, 37 re2/cs /an7 pin .............................................. 9, 36, 37 trise register .......................................................... 35 porte register ........................................................ 13, 126 postscaler, timer2 select (toutps3:toutps0 bits) ............................ 45 postscaler, wdt ................................................................ 39 assignment (psa bit) .......................................... 17, 39 block diagram ............................................................ 40 rate select (ps2:ps0 bits) ................................. 17, 39 switching between timer0 and wdt ........................ 40 power-on reset (por) .................... 127, 131, 132, 133, 134 oscillator start-up timer (ost) ....................... 127, 132 por status (por bit) ................................................ 23 power control (pcon) register .............................. 133 power-down (pd bit) ................................................. 16 power-on reset circuit, external ............................. 132 power-up timer (pwrt) ................................. 127, 132 time-out (to bit) ....................................................... 16 time-out sequence .................................................. 133 time-out sequence on power-up .................... 135, 136 pr2 register ...................................................................... 14 prescaler, capture ............................................................. 48 prescaler, timer0 ............................................................... 39 assignment (psa bit) .......................................... 17, 39 block diagram ............................................................ 40 rate select (ps2:ps0 bits) ................................. 17, 39 switching between timer0 and wdt ........................ 40 prescaler, timer1 ............................................................... 42 select (t1ckps1:t1ckps0 bits) .............................. 41 prescaler, timer2 ............................................................... 50 select (t2ckps1:t2ckps0 bits) .............................. 45 pro mate ii universal programmer ............................ 145 product identification system ........................................... 199 program counter pcl register .............................................................. 24 pclath register .............................................. 24, 138 reset conditions ...................................................... 133 program memory ............................................................... 11 interrupt vector .......................................................... 11 paging .................................................................. 11, 24 program memory map ............................................... 11 reset vector .............................................................. 11 program verification ......................................................... 141 programming pin (vpp) .................................................... 7, 8 programming, device instructions ................................... 143 pwm (ccp module) .......................................................... 50 block diagram ........................................................... 50 ccpr1h:ccpr1l registers ..................................... 50 duty cycle ................................................................. 50 example frequencies/resolutions ............................ 51 output diagram ......................................................... 50 period ........................................................................ 50 set-up for pwm operation ........................................ 51 tmr2 to pr2 match ............................................ 45, 50 tmr2 to pr2 match enable (tmr2ie bit) ................ 19 tmr2 to pr2 match flag (tmr2if bit) ..................... 20 q q-clock .............................................................................. 50 r r/w .................................................................................... 54 r/w bit ............................................................................... 64 r/w bit ............................................................................... 65 rce,receive enable bit, rce ........................................... 56 rcreg .............................................................................. 15 rcsta register .......................................................... 15, 98 cren bit ................................................................... 98 ferr bit .................................................................... 98 oerr bit ................................................................... 98 rx9 bit ...................................................................... 98 rx9d bit .................................................................... 98 spen bit .............................................................. 97, 98 sren bit ................................................................... 98 read/write bit, r/w ........................................................... 54 receive overflow indicator bit, sspov ............................. 55 register file ....................................................................... 11 register file map ............................................................... 12 registers fsr summary ........................................................... 15 indf summary ........................................................... 15 intcon summary ........................................................... 15 pcl summary ........................................................... 15 pclath summary ........................................................... 15 portb summary ........................................................... 15 sspstat .................................................................. 54 status summary ........................................................... 15 summary ................................................................... 13 tmr0 summary ........................................................... 15 trisb summary ........................................................... 15 reset ....................................................................... 127, 131 block diagram ......................................................... 131 reset conditions for all registers ........................... 134 reset conditions for pcon register ...................... 133 reset conditions for program counter .................... 133 reset conditions for status register ................... 133 restart condition enabled bit, rse ................................... 56 revision history ............................................................... 187 rse ................................................................................... 56
pic16c77x ? 1999 microchip technology inc. preliminary ds30275a-page 193 s sae .................................................................................... 56 sck .................................................................................... 57 scl .................................................................................... 64 sda .................................................................................... 64 sdi ..................................................................................... 57 sdo ................................................................................... 57 seeval evaluation and programming system ............ 147 serial clock, sck .............................................................. 57 serial clock, scl ............................................................... 64 serial data address, sda .................................................. 64 serial data in, sdi ............................................................. 57 serial data out, sdo ......................................................... 57 slave select synchronization ............................................ 60 slave select, ss ................................................................ 57 sleep ............................................................. 127, 131, 140 smp ................................................................................... 54 software simulator (mplab-sim) ................................... 147 spbrg register ................................................................ 14 spe .................................................................................... 56 special features of the cpu ........................................... 127 special function registers ................................................ 13 pic16c73 .................................................................. 13 pic16c73a ................................................................ 13 pic16c74 .................................................................. 13 pic16c74a ................................................................ 13 pic16c76 .................................................................. 13 pic16c77 .................................................................. 13 speed, operating ................................................................. 1 spi master mode .............................................................. 59 serial clock ................................................................ 57 serial data in ............................................................. 57 serial data out .......................................................... 57 serial peripheral interface (spi) ................................ 53 slave select ............................................................... 57 spi clock .................................................................... 59 spi mode ................................................................... 57 spi clock edge select, cke ............................................. 54 spi data input sample phase select, smp ...................... 54 spi master/slave connection ............................................ 58 spi module master/slave connection ........................................... 58 slave mode ................................................................ 60 slave select synchronization .................................... 60 slave synch timnig ................................................... 60 ss ...................................................................................... 57 ssp .................................................................................... 53 block diagram (spi mode) ........................................ 57 enable (sspie bit) ..................................................... 19 flag (sspif bit) ......................................................... 20 ra5/ss /an4 pin .......................................................... 8 rc3/sck/scl pin ................................................... 7, 9 rc4/sdi/sda pin .................................................... 7, 9 rc5/sdo pin ........................................................... 7, 9 spi mode ................................................................... 57 sspadd .................................................................... 64 sspbuf ............................................................... 59, 64 sspcon1 .................................................................. 55 sspcon2 .................................................................. 56 sspsr ................................................................. 59, 64 sspstat ............................................................. 54, 64 tmr2 output for clock shift ................................ 45, 46 ssp i 2 c ssp i 2 c operation ..................................................... 63 ssp module spi master mode ....................................................... 59 spi master./slave connection ................................... 58 spi slave mode ......................................................... 60 sspcon1 register ................................................... 63 ssp overflow detect bit, sspov ...................................... 64 sspadd register .............................................................. 14 sspbuf ...................................................................... 15, 64 sspbuf register .............................................................. 13 sspcon register ............................................................. 13 sspcon1 ................................................................... 55, 63 sspcon2 ......................................................................... 56 sspen .............................................................................. 55 sspif ................................................................................ 65 sspm3:sspm0 ................................................................. 55 sspov .................................................................. 55, 64, 82 sspstat .................................................................... 54, 64 sspstat register ............................................................ 14 stack .................................................................................. 24 start bit (s) ........................................................................ 54 start condition enabled bit, sae ....................................... 56 status register ...................................................... 16, 138 c bit ........................................................................... 16 dc bit ........................................................................ 16 irp bit ....................................................................... 16 pd bit ........................................................................ 16 rp1:rp0 bits ............................................................. 16 to bit ........................................................................ 16 z bit ........................................................................... 16 stop bit (p) ......................................................................... 54 stop condition enable bit .................................................. 56 synchronous serial port .................................................... 53 synchronous serial port enable bit, sspen ..................... 55 synchronous serial port mode select bits, sspm3:sspm0 ................................................................. 55 t t1con .............................................................................. 15 t1con register .......................................................... 15, 41 t1ckps1:t1ckps0 bits ........................................... 41 t1oscen bit ............................................................ 41 t1sync bit ............................................................... 41 tmr1cs bit ............................................................... 41 tmr1on bit .............................................................. 41 t2con register .......................................................... 15, 45 t2ckps1:t2ckps0 bits ........................................... 45 tmr2on bit .............................................................. 45 toutps3:toutps0 bits ......................................... 45 timer0 ............................................................................... 39 block diagram ........................................................... 39 clock source edge select (t0se bit) ................. 17, 39 clock source select (t0cs bit) .......................... 17, 39 overflow enable (t0ie bit) ........................................ 18 overflow flag (t0if bit) .................................... 18, 138 overflow interrupt .............................................. 40, 138 ra4/t0cki pin, external clock ............................... 7, 8 timer1 ............................................................................... 41 block diagram ........................................................... 42 capacitor selection ................................................... 43 clock source select (tmr1cs bit) ........................... 41 external clock input sync (t1sync bit) ................... 41 module on/off (tmr1on bit) ................................... 41 oscillator .............................................................. 41, 43 oscillator enable (t1oscen bit) .............................. 41 overflow enable (tmr1ie bit) .................................. 19 overflow flag (tmr1if bit) ....................................... 20
pic16c77x ds30275a-page 194 preliminary ? 1999 microchip technology inc. overflow interrupt ................................................ 41, 43 rc0/t1oso/t1cki pin ........................................... 7, 9 rc1/t1osi/ccp2 pin .............................................. 7, 9 special event trigger (ccp) ................................ 43, 49 t1con register ........................................................ 41 tmr1h register ........................................................ 41 tmr1l register ......................................................... 41 timer2 block diagram ............................................................ 46 pr2 register ........................................................ 45, 50 ssp clock shift .................................................... 45, 46 t2con register ........................................................ 45 tmr2 register ........................................................... 45 tmr2 to pr2 match enable (tmr2ie bit) ................ 19 tmr2 to pr2 match flag (tmr2if bit) ..................... 20 tmr2 to pr2 match interrupt ........................ 45, 46, 50 timing diagrams acknowledge sequence timing ................................. 85 baud rate generator with clock arbitration .............. 73 brg reset due to sda collision .............................. 92 brown-out reset ...................................................... 163 bus collision start condition timing ....................................... 91 bus collision during a restart condition (case 1) .... 93 bus collision during a restart condition (case2) ..... 93 bus collision during a start condition (scl = 0) ...... 92 bus collision during a stop condition ....................... 94 bus collision for transmit and acknowledge ............. 90 capture/compare/pwm ........................................... 169 clkout and i/o ...................................................... 162 external clock timing .............................................. 161 i 2 c master mode first start bit timing ........................ 74 i 2 c master mode reception timing ............................ 84 i 2 c master mode transmission timing ....................... 81 master mode transmit clock arbitration .................... 89 power-up timer ....................................................... 163 repeat start condition ............................................... 76 reset ........................................................................ 163 slave synchronization ............................................... 60 start-up timer .......................................................... 163 stop condition receive or transmit .......................... 87 time-out sequence on power-up .................... 135, 136 timer0 ...................................................................... 168 timer1 ...................................................................... 168 usart asynchronous master transmission ........... 103 usart synchronous receive ................................. 171 usart synchronous reception .............................. 109 usart synchronous transmission ................ 108, 171 usart, asynchronous reception ........................... 105 wake-up from sleep via interrupt .......................... 141 watchdog timer ....................................................... 163 tmr0 ................................................................................. 15 tmr0 register ................................................................... 13 tmr1h ............................................................................... 15 tmr1h register ................................................................ 13 tmr1l ............................................................................... 15 tmr1l register ................................................................. 13 tmr2 ................................................................................. 15 tmr2 register ................................................................... 13 trisa register .......................................................... 14, 126 trisb register .......................................................... 14, 126 trisc register .................................................................. 14 trisd register .................................................................. 14 trise register .................................................... 14, 35, 126 ibf bit ........................................................................ 35 ibov bit ..................................................................... 35 obf bit ...................................................................... 35 pspmode bit ................................................ 34, 35, 37 txreg .............................................................................. 15 txsta register ................................................................. 97 brgh bit ............................................................. 97, 99 csrc bit ................................................................... 97 sync bit ................................................................... 97 trmt bit .................................................................... 97 tx9 bit ....................................................................... 97 tx9d bit .................................................................... 97 txen bit .................................................................... 97 u ua ...................................................................................... 54 universal synchronous asynchronous receiver transmitter (usart) asynchronous receiver setting up reception ....................................... 104 timing diagram ............................................... 105 update address, ua .......................................................... 54 usart ............................................................................... 97 asynchronous mode ................................................ 102 master transmission ....................................... 103 receive block diagram ................................... 105 transmit block diagram .................................. 102 baud rate generator (brg) ..................................... 99 baud rate error, calculating ............................. 99 baud rate formula ........................................... 99 baud rates, asynchronous mode (brgh=0) . 100 baud rates, asynchronous mode (brgh=1) . 101 baud rates, synchronous mode ..................... 100 high baud rate select (brgh bit) ............. 97, 99 sampling ............................................................ 99 clock source select (csrc bit) ................................ 97 continuous receive enable (cren bit) .................... 98 framing error (ferr bit) .......................................... 98 mode select (sync bit) ............................................ 97 overrun error (oerr bit) .......................................... 98 rc6/tx/ck pin ........................................................ 7, 9 rc7/rx/dt pin ........................................................ 7, 9 rcsta register ........................................................ 98 receive data, 9th bit (rx9d bit) ............................... 98 receive enable (rcie bit) ........................................ 19 receive enable, 9-bit (rx9 bit) ................................. 98 receive flag (rcif bit) ............................................. 20 serial port enable (spen bit) ............................. 97, 98 single receive enable (sren bit) ............................ 98 synchronous master mode ...................................... 107 reception ........................................................ 109 transmission ................................................... 108 synchronous slave mode ........................................ 110 transmit data, 9th bit (tx9d) ................................... 97 transmit enable (txen bit) ...................................... 97 transmit enable (txie bit) ........................................ 19 transmit enable, nine-bit (tx9 bit) ........................... 97 transmit flag (txie bit) ............................................ 20 transmit shift register status (trmt bit) ................ 97 txsta register ......................................................... 97
pic16c77x ? 1999 microchip technology inc. preliminary ds30275a-page 195 w w register ....................................................................... 138 wake-up from sleep .............................................. 127, 140 interrupts .......................................................... 133, 134 mclr reset ............................................................ 134 timing diagram ........................................................ 141 wdt reset .............................................................. 134 watchdog timer (wdt) ........................................... 127, 139 block diagram .......................................................... 139 enable (wdte bit) ................................................... 139 programming considerations .................................. 139 rc oscillator ............................................................ 139 time-out period ....................................................... 139 wdt reset, normal operation ................ 131, 133, 134 wdt reset, sleep ......................................... 133, 134 waveform for general call address sequence ................. 69 wcol .................................................. 55, 74, 79, 82, 85, 87 wcol status flag ............................................................. 74 write collision detect bit, wcol ....................................... 55 www, on-line support ...................................................... 4
pic16c77x ds30275a-page 196 preliminary ? 1999 microchip technology inc. bit/register cross-reference list adcs1:adcs0 ..................................adcon0<7:6> adie ...................................................pie1<6> adif ...................................................pir1<6> adon .................................................adcon0<0> bf .......................................................sspstat<0> bor ...................................................pcon<0> brgh .................................................txsta<2> c .........................................................status<0> ccp1ie ..............................................pie1<2> ccp1if ..............................................pir1<2> ccp1m3:ccp1m0 .............................ccp1con<3:0> ccp1x:ccp1y ..................................ccp1con<5:4> ccp2ie ..............................................pie2<0> ccp2if ..............................................pir2<0> ccp2m3:ccp2m0 .............................ccp2con<3:0> ccp2x:ccp2y ..................................ccp2con<5:4> chs2:chs0 .......................................adcon0<5:3> cke ....................................................sspstat<6> ckp ....................................................sspcon<4> cren .................................................rcsta<4> csrc .................................................txsta<7> d/a .....................................................sspstat<5> dc ......................................................status<1> ferr .................................................rcsta<2> gie .....................................................intcon<7> go/done ..........................................adcon0<2> ibf ......................................................trise<7> ibov ...................................................trise<5> inte ...................................................intcon<4> intedg ..............................................option_reg<6> intf ...................................................intcon<1> irp .....................................................status<7> obf ....................................................trise<6> oerr .................................................rcsta<1> p .........................................................sspstat<4> pcfg2:pcfg0 ..................................adcon1<2:0> pd ......................................................status<3> peie ...................................................intcon<6> por ...................................................pcon<1> ps2:ps0 .............................................option_reg<2:0> psa ....................................................option_reg<3> pspie .................................................pie1<7> pspif .................................................pir1<7> pspmode .........................................trise<4> r/w ....................................................sspstat<2> rbie ...................................................intcon<3> rbif ...................................................intcon<0> rbpu .................................................option_reg<7> rcie ...................................................pie1<5> rcif ...................................................pir1<5> rp1:rp0 ............................................status<6:5> rx9 ....................................................rcsta<6> rx9d ..................................................rcsta<0> s .........................................................sspstat<3> smp ...................................................sspstat<7> spen .................................................rcsta<7> sren .................................................rcsta<5> sspen ...............................................sspcon<5> sspie .................................................pie1<3> sspif .................................................pir1<3> sspm3:sspm0 ..................................sspcon<3:0> sspov ...............................................sspcon<6> sync .................................................txsta<4> t0cs .................................................. option_reg<5> t0ie ................................................... intcon<5> t0if ................................................... intcon<2> t0se .................................................. option_reg<4> t1ckps1:t1ckps0 .......................... t1con<5:4> t1oscen .......................................... t1con<3> t1sync ............................................. t1con<2> t2ckps1:t2ckps0 .......................... t2con<1:0> tmr1cs ............................................ t1con<1> tmr1ie .............................................. pie1<0> tmr1if .............................................. pir1<0> tmr1on ............................................ t1con<0> tmr2ie .............................................. pie1<1> tmr2if .............................................. pir1<1> tmr2on ............................................ t2con<2> to ...................................................... status<4> toutps3:toutps0 ......................... t2con<6:3> trmt ................................................. txsta<1> tx9 .................................................... txsta<6> tx9d .................................................. txsta<0> txen ................................................. txsta<5> txie ................................................... pie1<4> txif ................................................... pir1<4> ua ...................................................... sspstat<1> wcol ................................................ sspcon<7> z ......................................................... status<2>
1998 microchip technology inc. ds30275a-page 197 pic16c77x systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-602-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmicro, picstart, picmaster and pro mate are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. flex rom, mplab and fuzzy- lab are trademarks and sqtp is a service mark of micro- chip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ?device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development sys- tems, technical information and more ? listing of seminars and events 981103
pic16c77x ds30275a-page 198 1998 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (602) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30275a pic16c77x
pic16c77x ? 1999 microchip technology inc. advance information ds30275a-page 199 pic16c77x product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. * jw devices are uv erasable and can be programmed to any device configuration. jw devices meet the electrical requirement of each oscillator type (including lc devices). sales and support part no. -xx x /xx xxx pattern package temperature range frequency range device device pic16c77x (1) , pic16c77xt (2) ;v dd range 4.0v to 5.5v pic16lc77x (1) , pic16lc77xt (2) ;v dd range 2.5v to 5.5v frequency range 04 = 4 mhz 20 = 20 mhz temperature range b (3) = 0 c to 70 c (commercial) i= -40 c to +85 c (industrial) package jw = windowed cerdip/ceramic pq = mqfp (metric pqfp) pt = tqfp (thin quad flatpack) so = soic sp = skinny plastic dip p=pdip l=plcc ss = ssop pattern qtp, sqtp, code or special requirements (blank otherwise) examples: g) pic16c774 -04/p 301 = commercial temp., pdip package, 4 mhz, normal v dd limits, qtp pattern #301. h) pic16lc773 - 04i/so = industrial temp., soic package, 200 khz, extended v dd limits. i) pic16c774 - 20i/p = industrial temp., pdip package, 20mhz, normal v dd limits. note 1: c = cmos lc = low power cmos t = in tape and reel - soic, ssop, plcc, mqfp, tqfp packages only. 2: b= blank data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (602) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or oth e r intellectual property rights arising from such use or otherwise. use of microchips products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. al l other trademarks mentioned herein are the property of their respective companies. ds30275a-page 200 ? 1999 microchip technology inc. all rights reserved. ? 1999 microchip technology incorporated. printed in the usa. 2/99 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602-786-7200 fax: 602-786-7277 technical support: 602-786-7627 web: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 972-991-7177 fax: 972-991-8588 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. 42705 grand river, suite 201 novi, mi 48375-1727 tel: 248-374-1888 fax: 248-374-2874 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 714-263-1888 fax: 714-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 516-273-5305 fax: 516-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia pacific rm 3801b, tower two metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yanan road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road ta i p e i , ta i wa n , ro c tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44-1189-21-5858 fax: 44-1189-21-5835 france arizona microchip technology sarl zone industrielle de la bonde 2 rue du buisson aux fraises 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 mnchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-39-6899939 fax: 39-39-6899883 02/10/99 w orldwide s ales and s ervice microchip received iso 9001 quality system certification for its worldwide headquarters, design, and wafer fabrication facilities in january, 1997. our field-programmable picmicro ? 8- bit mcus, k ee l oq ? code hopping devices, serial eeproms, related specialty memory products and devel- opment systems conform to the strin- gent quality standards of the international standard organization (iso).

▲Up To Search▲

Price & Availability of PIC16LC773-20IP

	To Download PIC16LC773-20IP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .